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The goal of this web page is to introduce you to using Sue in making and
using hierarchy to efficiently design your layouts. The use of hierarchy is
paramount to the design of VLSI, therefore, learning this technique is critical.
Portions of this web page were copied from
http://www.stanford.edu/class/ee272/ Manually draw datapath schematics from your verilog. Create an irsim schematic netlist. Create a full-chip netlist that can be used for macro-cell place and route. Example: Entering a carry-select comparator in SUE
First, enter the two basic cells needed to implement a carry-select comparator (the carry cell and the 2-input mux) as shown below. You will find the following short-cut keys helpful when drawing carry.sue and mux2.sue:
New Schematic: Ctl-n Selection: Left Mouse Move: Middle Mouse Duplicate: d Delete: q Rotate: r Wiring: w
Don't forget to change the width of the transistors.
Next, enter the block diagram for carry.sue and mux2.sue as shown below. You may find the following short-cut keys helpful: Make block view: Shift-c Shift to other view: c Line/rect: l Add text: t Change text size: Double-click on text: Shift-Left Mouse, Shift-Middle Mouse, Shift-Right Mouse
Using carry.sue draw the schematic and block view for comp3.sue.
Using comp3.sue draw the schematic and block view for comp3sel.sue. You may find the following short-cut keys helpful: Zoom in: z Zoom out: Shift-z
The comparator is now done. Using comp3.sue and comp3sel.sue draw the schematic for comp9.sue. After drawing the schematic create the block view and notice that if you were to use this block you would only need to draw two buses (a_b[8:0],b[8:0]) as opposed to 16 individual wires. If you don't use name_net_s to name [8], [7], etc, then you won't get a correct netlist!
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Oklahoma State University |
