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Netgen is a program for comparing circuit netlists. Normally it is used to verify circuit layout by comparing a netlist extracted from a circuit layout to a specification netlist that is assumed to be correct. This kind of verification is commonly known as LVS (layout versus schematic). You will use Netgen to compare the netlist generated from Sue (based on the schematic) with the one generated from Magic by ext2sim (based on the layout).
Running Netgen
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Netgen is significantly disadvantaged, because it has a hard time with the orientation of transistors
that have mirrored ports. MOSFETs have this problem and so its a good idea to correct for this problem
before comparing two circuits.
Lucikly, netgen has a fix for this and so its important to type this command before running LVS.
permute transistors
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Netgen has a script-level procedure "lvs" which takes care of the above
sequence of commands, as well as dumping the majority of the output to an
output file, and reporting only the final analysis in the console window.
The syntax of this command is:
lvs
<filename1> <filename2> [<logfilename>]
If "logfilename" is not specified, then the default filename "comp.out" will
be used.
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Interpreting the output:
Illegal fragments are generated around areas where the netlists cannot be
resolved. The worst matches will be listed at the top, which is usually the
place to start looking.
Connectivity of elements and nodes can be traced with commands:
nodes <element_name>
<cellname>
elements <node_name> <cellname>
Where
cellname
is the filename (one of the two files loaded for comparison). The
elements
command prints all of the elements (transistors, capacitors, resistors,
etc.) connected to a specific named node. The
nodes
command prints the node names for each pin of the specified element. For
".sim" netlists containing position information for each transistor, all
transistor elements (and some non-transistor elements such as poly-poly
capacitors and rpoly resistors extracted from magic) will have names like
"n@45,376" indicating an n-type transistor at position x=45, y=376 on the
layout. This naming convention permits tracing errors back to the layout and
schematic.
Netgen ignores all lines in the .sim file that begin with A, B, R,
v and semicolon. There are also a variety of options that can be specified on
the command line. For a full list of options see
Netgen manual page.
Netgen produces certain
information about the circuits (e.g., number of devices, number of nets) and
tries to match all the nodes.
The comparison is successful if you get the
message:
Circuits match uniquely.
LVS done.
If the comparison fails, you will get
the error message (e.g. Graphs do not match, Node mismatch etc.)
If you get this message you should go
back and check your layout for functional differences from the schematic.
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