Oklahoma State University System on Chip (SoC) Design Flows

Design Flows for use with Magic, Cadence, Synopsys, and MOSIS


The following pages give information regarding design flows for System on Chip designs that were developed for use at Oklahoma State University for use with MOSIS SCMOS_SUBM process.

We have also developed jointly with North Carolina State University FreePDK45nm, a Variation-Aware 45nm Design Flow for the Semiconductor Research Corporation. The SRC version is designed with Synopsys’ Cadabra and allows full-chip synthesis and place & route through CDS Encounter. You can download the design flow and standard cell library here and the technology kit from North Carolina State University.

Supported Technologies:

  • AMI 0.5um (with pad cells)
  • AMI 0.35um (with pad cells)
  • TSMC 0.25um
  • TSMC 0.18um
  • FreePDK 45nm

Provided files:

  • Timing Libraries: LIB, DB, TLF
  • Simulation Libraries: Verilog, VHDL
  • Geometry Libraries: LEF, FRAM
  • Cell layouts: Virtuoso, Magic, GDS2, CIF

Please follow download link : http://vlsiarch.ecen.okstate.edu/flows

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