This site discusses some of the tools related to our research group.

High Radix Divide/Multiply Architectures using Scaling

These designs discuss the implementations within the architecture for our radix 512 divide and
combined divide and multiply that was discussed during 2010 Asilomar Conference on Signals, Systems, and Computers.

• PowerPoint Slides (pptx) (pdf)
• 32-bit Plain Verilog files with SBTM (zip)
• 32-bit Modified Verilog files with no CPA and SBTM (zip)
• 32-bit Modified Verilog files with SBTM and Multiply capability (zip)

Optimized Multipartite Table Methods and SBTM/STAM

This research presents an optimization method for computing an optimum lookup table size for two well-known look up table elementary function approximation methods; Symmetric Table Additional Method (STAM) and Multipartite Table Method (MTM). Using a discrete optimization algorithm called Leapfrogging, this paper utilizes a method to find the best decomposition of the coefficients to optimize look up table sizes. The resulting designs can easily be utilized for any approximation for functions with significantly smaller requirements for lookup table sizes. Results show that the proposed optimized method is able to achieve higher memory efficiency than the best existing MTM. For sine function, optimized method saves 85.29% of memory for 16-bit accuracy and 53.89% for 24-bit accuracy when comparing to the best existing result obtained by the unified Multipartite Table Method.

Note: Scripts and Verilog Files for oMTM will become available when the paper is accepted for publication

• PowerPoint Slides (pptx) (pdf)
• MATLAB files to utilize leapfrogging method
• SBTM/STAM C++ code
• Generator for System Verilog implementations