Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

SubTree from clk
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [291.9(ps) 305.6(ps)] 13.7(ps) [291.8(ps) 305.8(ps)] 14(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
p11/YPAD 28 [291.9(ps) 305.6(ps)] 13.7(ps) [291.8(ps) 305.8(ps)] 14(ps)



SubTree from p11/DI
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [291.9(ps) 305.6(ps)] 13.7(ps) [291.8(ps) 305.8(ps)] 14(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew


clk (0 0) load=0.636903(pf)

p11/YPAD (0.0051 0.0051)
p11/DI (0.2675 0.2688) load=0.797727(pf)

core_block_control_CURRENT_reg_3/CLK (0.3042 0.3044)

core_block_control_CURRENT_reg_2/CLK (0.3056 0.3058)

core_block_control_CURRENT_reg_1/CLK (0.3053 0.3055)

core_block_control_CURRENT_reg_0/CLK (0.3051 0.3053)

core_block_acc_q_reg_7/CLK (0.3007 0.3008)

core_block_acc_q_reg_6/CLK (0.301 0.3011)

core_block_acc_q_reg_5/CLK (0.3009 0.301)

core_block_acc_q_reg_4/CLK (0.3007 0.3007)

core_block_acc_q_reg_3/CLK (0.2995 0.2996)

core_block_acc_q_reg_2/CLK (0.2991 0.2991)

core_block_acc_q_reg_1/CLK (0.2997 0.2998)

core_block_acc_q_reg_0/CLK (0.2994 0.2994)

core_block_divider_regiB_q_reg_7/CLK (0.2971 0.297)

core_block_divider_regiB_q_reg_6/CLK (0.2976 0.2976)

core_block_divider_regiB_q_reg_5/CLK (0.2965 0.2965)

core_block_divider_regiB_q_reg_4/CLK (0.2965 0.2965)

core_block_divider_regiB_q_reg_3/CLK (0.2956 0.2956)

core_block_divider_regiB_q_reg_2/CLK (0.2933 0.2932)

core_block_divider_regiB_q_reg_1/CLK (0.2931 0.293)

core_block_divider_regiB_q_reg_0/CLK (0.293 0.2928)

core_block_divider_regiA_q_reg_7/CLK (0.2977 0.2977)

core_block_divider_regiA_q_reg_6/CLK (0.2968 0.2967)

core_block_divider_regiA_q_reg_5/CLK (0.2968 0.2968)

core_block_divider_regiA_q_reg_4/CLK (0.2928 0.2926)

core_block_divider_regiA_q_reg_3/CLK (0.2919 0.2918)

core_block_divider_regiA_q_reg_2/CLK (0.2978 0.2977)

core_block_divider_regiA_q_reg_1/CLK (0.2956 0.2955)

core_block_divider_regiA_q_reg_0/CLK (0.2961 0.296)