Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

SubTree from clk
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [217(ps) 245.1(ps)] 28.1(ps) [229.3(ps) 256.9(ps)] 27.6(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
p11/YPAD 28 [217(ps) 245.1(ps)] 28.1(ps) [229.3(ps) 256.9(ps)] 27.6(ps)



SubTree from p11/DI
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [217(ps) 245.1(ps)] 28.1(ps) [229.3(ps) 256.9(ps)] 27.6(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew


clk (0 0) load=0.450181(pf)

p11/YPAD (0.0036 0.0036)
p11/DI (0.2027 0.2152) load=0.824782(pf)

core_block_control_CURRENT_reg_3/CLK (0.2451 0.2569)

core_block_control_CURRENT_reg_2/CLK (0.2436 0.2555)

core_block_control_CURRENT_reg_1/CLK (0.244 0.2559)

core_block_control_CURRENT_reg_0/CLK (0.2449 0.2568)

core_block_acc_q_reg_7/CLK (0.237 0.249)

core_block_acc_q_reg_6/CLK (0.2327 0.2449)

core_block_acc_q_reg_5/CLK (0.2358 0.2479)

core_block_acc_q_reg_4/CLK (0.2314 0.2435)

core_block_acc_q_reg_3/CLK (0.226 0.2382)

core_block_acc_q_reg_2/CLK (0.217 0.2293)

core_block_acc_q_reg_1/CLK (0.2243 0.2365)

core_block_acc_q_reg_0/CLK (0.2278 0.2399)

core_block_divider_regiB_q_reg_7/CLK (0.2364 0.2485)

core_block_divider_regiB_q_reg_6/CLK (0.2356 0.2477)

core_block_divider_regiB_q_reg_5/CLK (0.2346 0.2467)

core_block_divider_regiB_q_reg_4/CLK (0.2375 0.2496)

core_block_divider_regiB_q_reg_3/CLK (0.2373 0.2494)

core_block_divider_regiB_q_reg_2/CLK (0.2293 0.2415)

core_block_divider_regiB_q_reg_1/CLK (0.236 0.248)

core_block_divider_regiB_q_reg_0/CLK (0.2332 0.2453)

core_block_divider_regiA_q_reg_7/CLK (0.234 0.2461)

core_block_divider_regiA_q_reg_6/CLK (0.2347 0.2467)

core_block_divider_regiA_q_reg_5/CLK (0.2331 0.2452)

core_block_divider_regiA_q_reg_4/CLK (0.2348 0.2468)

core_block_divider_regiA_q_reg_3/CLK (0.242 0.2539)

core_block_divider_regiA_q_reg_2/CLK (0.2342 0.2463)

core_block_divider_regiA_q_reg_1/CLK (0.2395 0.2515)

core_block_divider_regiA_q_reg_0/CLK (0.2383 0.2503)