Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
6.5(ps) ~ 7.92(ps)
1
7.92(ps) ~ 9.34(ps)
0
9.34(ps) ~ 10.76(ps)
3
10.76(ps) ~ 12.18(ps)
5
12.18(ps) ~ 13.6(ps)
1
13.6(ps) ~ 15.02(ps)
6
15.02(ps) ~ 16.44(ps)
2
16.44(ps) ~ 17.86(ps)
1
17.86(ps) ~ 19.28(ps)
3
19.28(ps) ~ 20.7(ps)
6
(max, min, avg, skew) = (20.7(ps) 6.5(ps) 14.9536(ps) 14.2(ps))






Detail Phase Delay Report

TOP LEVEL:
clk (0 0)

LEVEL 1:
cellName = DFFSR
block_control_CURRENT_reg_3/CLK (0.0118 0.0118)
cellName = DFFSR
block_control_CURRENT_reg_2/CLK (0.0108 0.0108)
cellName = DFFSR
block_control_CURRENT_reg_1/CLK (0.0105 0.0105)
cellName = DFFSR
block_control_CURRENT_reg_0/CLK (0.0115 0.0115)
cellName = DFFSR
block_acc_q_reg_7/CLK (0.0171 0.0171)
cellName = DFFSR
block_acc_q_reg_6/CLK (0.0182 0.0182)
cellName = DFFSR
block_acc_q_reg_5/CLK (0.0181 0.0181)
cellName = DFFSR
block_acc_q_reg_4/CLK (0.0106 0.0106)
cellName = DFFSR
block_acc_q_reg_3/CLK (0.0065 0.0065)
cellName = DFFSR
block_acc_q_reg_2/CLK (0.0097 0.0097)
cellName = DFFSR
block_acc_q_reg_1/CLK (0.012 0.012)
cellName = DFFSR
block_acc_q_reg_0/CLK (0.012 0.012)
cellName = DFFSR
block_divider_regiB_q_reg_7/CLK (0.0154 0.0154)
cellName = DFFSR
block_divider_regiB_q_reg_6/CLK (0.0194 0.0194)
cellName = DFFSR
block_divider_regiB_q_reg_5/CLK (0.0198 0.0198)
cellName = DFFSR
block_divider_regiB_q_reg_4/CLK (0.0159 0.0159)
cellName = DFFSR
block_divider_regiB_q_reg_3/CLK (0.0142 0.0142)
cellName = DFFSR
block_divider_regiB_q_reg_2/CLK (0.0131 0.0131)
cellName = DFFSR
block_divider_regiB_q_reg_1/CLK (0.0145 0.0145)
cellName = DFFSR
block_divider_regiB_q_reg_0/CLK (0.0145 0.0145)
cellName = DFFSR
block_divider_regiA_q_reg_7/CLK (0.0207 0.0207)
cellName = DFFSR
block_divider_regiA_q_reg_6/CLK (0.0189 0.0189)
cellName = DFFSR
block_divider_regiA_q_reg_5/CLK (0.0207 0.0207)
cellName = DFFSR
block_divider_regiA_q_reg_4/CLK (0.0205 0.0205)
cellName = DFFSR
block_divider_regiA_q_reg_3/CLK (0.0202 0.0202)
cellName = DFFSR
block_divider_regiA_q_reg_2/CLK (0.0143 0.0143)
cellName = DFFSR
block_divider_regiA_q_reg_1/CLK (0.0137 0.0137)
cellName = DFFSR
block_divider_regiA_q_reg_0/CLK (0.0141 0.0141)