/**************************************************/
/* Compile Script for Synopsys                    */
/*                                                */
/* dc_shell -f compile_dc.scr                     */
/*                                                */
/* Johannes Grad, OSU                             */
/* jgrad@ece.osu.edu                              */
/**************************************************/

/* All verilog files, separated by spaces  */
my_verilog_files = 	{FILE1.v FILE2.v}

/* Top-level Module  */
my_toplevel = 	 	TOP_LEVEL_MODULE

/* The name of the clock pin. If no clock-pin  */
/* exists, pick anything  */
my_clock_pin = 		clk

/* Target frequency in MHz for optimization  */
my_clk_freq_MHz = 	50

/* Delay of input signals (Clock-to-Q, Package etc.)  */
my_input_delay_ns = 	1

/* Reserved time for output signals (Holdtime etc.)  */
my_output_delay_ns = 	1


/**************************************************/
/* No modifications needed below                  */
/* except to insert pads                          */
/**************************************************/

OSUcells = get_unix_variable("OSUcells") + "/lib/tsmc025/lib"
search_path=search_path + OSUcells

link_library=target_library={osu025_stdcells.db}+{dw_foundation.sldb}
target_library="osu025_stdcells.db"
define_design_lib WORK -path ./WORK
verilogout_show_unconnected_pins = "true"
set_ultra_mode true
set_ultra_optimization -force

analyze -f verilog my_verilog_files

elaborate my_toplevel

current_design my_toplevel

link
uniquify

my_period = 1000 / my_clk_freq_MHz

if (find(port, my_clock_pin) == {my_clock_pin}) { 
	clk_name = my_clock_pin
	create_clock -period my_period clk_name
}

if (find(port, my_clock_pin) == {}) { 
	clk_name = vclk 
	create_clock -period my_period -name clk_name
}

set_driving_cell -cell INVX8 all_inputs()
set_input_delay my_input_delay_ns -clock clk_name all_inputs() - my_clock_pin
set_output_delay my_output_delay_ns -clock clk_name all_outputs()

compile -ungroup_all -map_effort medium

compile -incremental_mapping -map_effort medium

check_design 
report_constraint -all_violators

filename = my_toplevel + ".vh"
write -f verilog -output filename

filename = my_toplevel + ".sdc"
write_sdc  filename

filename = my_toplevel + ".db"
write -hier -output filename

report_timing > timing.rep
report_cell   > cell.rep
report_power  > power.rep

quit