Index of /flows/MOSIS_SCMOS/latest

Name	Last modified	Size

Parent Directory		-
synopsys/	2017-01-22 15:44	-
osu_soc_v2.7.tar.gz	2017-01-22 15:44	17M
cadence/	2017-01-22 15:44	-
OSU_Copyright	2017-01-22 15:44	1.4K

FreePDK: Unleashing VLSI to the Masses

System-on-Chip Designs for SCMOS MOSIS AMI 0.6um, AMI 0.35um, TSMC 0.25um, and TSMC 0.18um

Welcome to System on Chip (SoC) Design Flows at Oklahoma State University for AMI 0.6um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um brought to you by the VLSI Computer Architecture Research Group group at the Oklahoma State University!

Release Notes

Libraries and flows in all three technologies, AMI 0.5um, TSMC 0.25um and TSMC 0.18um are now availbale for both Cadence and Synopsys flows.
Please note that pads are only available for AMI 0.5um.
New for Version 2.7
- Library: Complete Synopsys and Cadence flows
- Flow: TSMC 0.18um and TSMC 0.25um flows are now available for Synopsys flow.
- Fixed bug in which a design with no pads didn't work in Synopsys flow.
- Added fat wire (minimum spacing for wide wires) rules for all technologies in Synopsys flow
- Adjusted power ring sizes for AMI 0.5 in Synopsys flow to improve initial DRC error count and improve routing.
- Modified OAI22X1 standard cell to satisfy fat wire rules.
All bugs, comments, questions, or any criticisms are highly encouraged. Please contact James Stine at james.stine@okstate.edu to contribute to the cause.