Index of /flows/MOSIS_SCMOS/iit_stdcells_v2.3beta

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[   ]iitcells_lib_2.3.tar.gz2017-01-22 15:44 7.0M 

Standard Cells for AMI 0.6um, AMI 0.35um, TSMC 0.25um, and TSMC 0.18um



Welcome to System on Chip (SoC) Design Flows at the Illinois Institute of Technology for AMI 0.6um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um brought to you by the VLSI Computer Architecture, Arithmetic, and CAD Research Group group at the Illinois Institute of Technology!

Portions of the tools here are funded in part by Cadence Design Systems, Inc.

This is Version 2.3 beta (5/21/05) Changes to the library: Only DF-II libraries changed: - added "functional" view with annotated verilog - added "abstract" view from LEF - added new "layout" view, now including all cell pins - added a 40pin LVS-clean padframe for AMI 0.5um

The release is split into 3 parts



All bugs, comments, questions, or any criticisms are highly encouraged. Please contact James Stine at jstine@ece.iit.edu to contribute to the cause.