Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
1.5(ps) ~ 1.5(ps)
1
(max, min, avg, skew) = (1.5(ps) 1.5(ps) 1.5(ps) 0(ps))

Output Delay RangeNumber of Buffer
342.2(ps) ~ 342.2(ps)
1
(max, min, avg, skew) = (342.2(ps) 342.2(ps) 342.2(ps) 0(ps))




Level 2
Input Delay Range Number of Buffer
345(ps) ~ 345.95(ps)
1
345.95(ps) ~ 346.9(ps)
6
346.9(ps) ~ 347.85(ps)
5
347.85(ps) ~ 348.8(ps)
6
348.8(ps) ~ 349.75(ps)
1
349.75(ps) ~ 350.7(ps)
1
350.7(ps) ~ 351.65(ps)
1
351.65(ps) ~ 352.6(ps)
2
352.6(ps) ~ 353.55(ps)
1
353.55(ps) ~ 354.5(ps)
4
(max, min, avg, skew) = (354.5(ps) 345(ps) 349.075(ps) 9.5(ps))






Detail Phase Delay Report

TOP LEVEL:
clk (0 0)

LEVEL 1:
cellName = CLKBUF2
clk__L1_I0/A (0.0015 0.0015)
clk__L1_I0/Y (0.3422 0.3439)

LEVEL 2:
cellName = DFFSR
block_divider/regiA/q_reg[0]/CLK (0.3462 0.3479)
cellName = DFFSR
block_divider/regiA/q_reg[2]/CLK (0.3464 0.3481)
cellName = DFFSR
block_divider/regiA/q_reg[1]/CLK (0.3463 0.348)
cellName = DFFSR
block_divider/regiA/q_reg[6]/CLK (0.346 0.3477)
cellName = DFFSR
block_divider/regiB/q_reg[7]/CLK (0.3469 0.3486)
cellName = DFFSR
block_divider/regiB/q_reg[6]/CLK (0.345 0.3467)
cellName = DFFSR
block_acc/q_reg[7]/CLK (0.3477 0.3494)
cellName = DFFSR
block_acc/q_reg[5]/CLK (0.3466 0.3483)
cellName = DFFSR
block_acc/q_reg[4]/CLK (0.3467 0.3484)
cellName = DFFSR
block_acc/q_reg[6]/CLK (0.3469 0.3486)
cellName = DFFSR
block_acc/q_reg[3]/CLK (0.347 0.3487)
cellName = DFFSR
block_divider/regiA/q_reg[7]/CLK (0.3494 0.3511)
cellName = DFFSR
block_divider/regiA/q_reg[5]/CLK (0.3478 0.3495)
cellName = DFFSR
block_divider/regiB/q_reg[3]/CLK (0.3481 0.3498)
cellName = DFFSR
block_divider/regiB/q_reg[5]/CLK (0.3481 0.3498)
cellName = DFFSR
block_divider/regiA/q_reg[4]/CLK (0.3482 0.3499)
cellName = DFFSR
block_divider/regiA/q_reg[3]/CLK (0.3483 0.35)
cellName = DFFSR
block_acc/q_reg[2]/CLK (0.3505 0.3522)
cellName = DFFSR
block_divider/regiB/q_reg[2]/CLK (0.3483 0.35)
cellName = DFFSR
block_divider/regiB/q_reg[4]/CLK (0.3483 0.35)
cellName = DFFSR
block_divider/regiB/q_reg[1]/CLK (0.3511 0.3528)
cellName = DFFSR
block_divider/regiB/q_reg[0]/CLK (0.3517 0.3534)
cellName = DFFSR
block_acc/q_reg[1]/CLK (0.3523 0.3539)
cellName = DFFSR
block_acc/q_reg[0]/CLK (0.3531 0.3548)
cellName = DFFSR
block_control/CURRENT_reg[1]/CLK (0.354 0.3556)
cellName = DFFSR
block_control/CURRENT_reg[2]/CLK (0.3543 0.356)
cellName = DFFSR
block_control/CURRENT_reg[0]/CLK (0.3544 0.3561)
cellName = DFFSR
block_control/CURRENT_reg[3]/CLK (0.3545 0.3562)