Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
1.5(ps) ~ 1.5(ps) | 1 |
(max, min, avg, skew) = (1.5(ps) 1.5(ps) 1.5(ps) 0(ps))
Output Delay Range | Number of Buffer |
348(ps) ~ 348(ps) | 1 |
(max, min, avg, skew) = (348(ps) 348(ps) 348(ps) 0(ps))
Level 2
Input Delay Range |
Number of Buffer |
352.1(ps) ~ 352.81(ps) | 4 |
352.81(ps) ~ 353.52(ps) | 3 |
353.52(ps) ~ 354.23(ps) | 0 |
354.23(ps) ~ 354.94(ps) | 1 |
354.94(ps) ~ 355.65(ps) | 1 |
355.65(ps) ~ 356.36(ps) | 3 |
356.36(ps) ~ 357.07(ps) | 4 |
357.07(ps) ~ 357.78(ps) | 7 |
357.78(ps) ~ 358.49(ps) | 1 |
358.49(ps) ~ 359.2(ps) | 4 |
(max, min, avg, skew) = (359.2(ps) 352.1(ps) 356.071(ps) 7.1(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = CLKBUF2
clk__L1_I0/A (0.0015 0.0015)
clk__L1_I0/Y (0.348 0.3492)
LEVEL 2:
cellName = DFFSR
block_divider/regiA/q_reg[0]/CLK (0.3521 0.3533)
cellName = DFFSR
block_divider/regiA/q_reg[2]/CLK (0.3523 0.3535)
cellName = DFFSR
block_divider/regiA/q_reg[1]/CLK (0.3522 0.3534)
cellName = DFFSR
block_divider/regiA/q_reg[6]/CLK (0.3521 0.3533)
cellName = DFFSR
block_divider/regiB/q_reg[7]/CLK (0.3531 0.3543)
cellName = DFFSR
block_divider/regiB/q_reg[6]/CLK (0.3529 0.3541)
cellName = DFFSR
block_acc/q_reg[7]/CLK (0.3533 0.3545)
cellName = DFFSR
block_acc/q_reg[5]/CLK (0.3562 0.3574)
cellName = DFFSR
block_acc/q_reg[4]/CLK (0.3563 0.3575)
cellName = DFFSR
block_acc/q_reg[6]/CLK (0.3565 0.3576)
cellName = DFFSR
block_acc/q_reg[3]/CLK (0.3567 0.3579)
cellName = DFFSR
block_divider/regiA/q_reg[7]/CLK (0.3544 0.3556)
cellName = DFFSR
block_divider/regiA/q_reg[5]/CLK (0.357 0.3582)
cellName = DFFSR
block_divider/regiB/q_reg[3]/CLK (0.3576 0.3588)
cellName = DFFSR
block_divider/regiB/q_reg[5]/CLK (0.3576 0.3588)
cellName = DFFSR
block_divider/regiA/q_reg[4]/CLK (0.3577 0.3589)
cellName = DFFSR
block_divider/regiA/q_reg[3]/CLK (0.3576 0.3588)
cellName = DFFSR
block_acc/q_reg[2]/CLK (0.3556 0.3568)
cellName = DFFSR
block_divider/regiB/q_reg[2]/CLK (0.3577 0.3589)
cellName = DFFSR
block_divider/regiB/q_reg[4]/CLK (0.3577 0.3589)
cellName = DFFSR
block_divider/regiB/q_reg[1]/CLK (0.3559 0.3571)
cellName = DFFSR
block_divider/regiB/q_reg[0]/CLK (0.3564 0.3576)
cellName = DFFSR
block_acc/q_reg[1]/CLK (0.3571 0.3583)
cellName = DFFSR
block_acc/q_reg[0]/CLK (0.3579 0.3591)
cellName = DFFSR
block_control/CURRENT_reg[1]/CLK (0.3588 0.36)
cellName = DFFSR
block_control/CURRENT_reg[2]/CLK (0.359 0.3602)
cellName = DFFSR
block_control/CURRENT_reg[0]/CLK (0.3591 0.3603)
cellName = DFFSR
block_control/CURRENT_reg[3]/CLK (0.3592 0.3604)