Index of /flows/MOSIS_SCMOS/iit_stdcells_v2.1

Name	Last modified	Size

Parent Directory		-
gds2_views_with_pins..>	2017-01-22 15:44	166K
iit_stdcells_flow_v2..>	2017-01-22 15:44	174K
iit_stdcells_lib_v2...>	2017-01-22 15:44	8.1M
iit_stdcells_ref_des..>	2017-01-22 15:44	59M

Standard Cells for AMI 0.6um, AMI 0.35um, TSMC 0.25um, and TSMC 0.18um

Welcome to System on Chip (SoC) Design Flows at the Illinois Institute of Technology for AMI 0.6um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um brought to you by the VLSI Computer Architecture, Arithmetic, and CAD Research Group group at the Illinois Institute of Technology!

Portions of the tools here are funded in part by Cadence Design Systems, Inc.

The release is now split into 3 parts

lib: The actual library files for all 4 technologies
flow: The scripts and documentation for the IIT ASIC flow
ref_designs: Reference Designs implemented in various tools on all technologies

All bugs, comments, questions, or any criticisms are highly encouraged. Please contact James Stine at jstine@ece.iit.edu to contribute to the cause.