A Framework for High-Level Synthesis of System-on-Chip Designs for
AMI 0.6um, AMI 0.35um, TSMC 0.25um, and TSMC 0.18um
The Perl scripts in this directory will generate RTL Verilog models of
truncated and non-truncated parallel carry-save array and Dadda tree
multipliers.
Input parameters:
-x the number of x bits
-y the number of y bits
-z the number of output bits
-k number of columns to keep
-m module name (optional)
The value of the multiplication, -x, and the multiplier, -y, are assumed to be used
in the non-truncated version to be -z=x+y. Any of the scripts (i.e. CCT, VCT, HCT) can
be used for non-truncated multipliers and should generate the same output. The Verilog
file tadders.v is needed to instantiate the lower-level RTL Verilog files produced by the
Perl scripts.
For example, an 8-bit by 8-bit carry-save
array multiplier would be generated with the following command:
array_v_CCT.pl -x 8 -y 8 -z 16
All bugs, comments, questions, or any criticisms are highly encouraged.
Please contact James Stine at
james.stine@okstate.edu to contribute to the cause.
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