Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
SubTree from clk
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[197.3(ps) 214.4(ps)] |
17.1(ps) |
[207.5(ps) 224.7(ps)] |
17.2(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
p11/YPAD |
28 |
[197.3(ps) 214.4(ps)] |
17.1(ps) |
[207.5(ps) 224.7(ps)] |
17.2(ps) |
SubTree from p11/DI
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[197.3(ps) 214.4(ps)] |
17.1(ps) |
[207.5(ps) 224.7(ps)] |
17.2(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
clk (0 0) load=0.450181(pf)
p11/YPAD (0.0036 0.0036)
p11/DI (0.1799 0.1905) load=0.83745(pf)
core_block_control_CURRENT_reg_3/CLK (0.2144 0.2247)
core_block_control_CURRENT_reg_2/CLK (0.2132 0.2235)
core_block_control_CURRENT_reg_1/CLK (0.2135 0.2238)
core_block_control_CURRENT_reg_0/CLK (0.2144 0.2247)
core_block_acc_q_reg_7/CLK (0.2131 0.2234)
core_block_acc_q_reg_6/CLK (0.2112 0.2214)
core_block_acc_q_reg_5/CLK (0.2129 0.2232)
core_block_acc_q_reg_4/CLK (0.2102 0.2204)
core_block_acc_q_reg_3/CLK (0.2052 0.2153)
core_block_acc_q_reg_2/CLK (0.1973 0.2075)
core_block_acc_q_reg_1/CLK (0.1996 0.2098)
core_block_acc_q_reg_0/CLK (0.2061 0.2163)
core_block_divider_regiB_q_reg_7/CLK (0.213 0.2233)
core_block_divider_regiB_q_reg_6/CLK (0.2122 0.2224)
core_block_divider_regiB_q_reg_5/CLK (0.2116 0.2218)
core_block_divider_regiB_q_reg_4/CLK (0.2139 0.2242)
core_block_divider_regiB_q_reg_3/CLK (0.2137 0.2239)
core_block_divider_regiB_q_reg_2/CLK (0.2044 0.2146)
core_block_divider_regiB_q_reg_1/CLK (0.2087 0.2189)
core_block_divider_regiB_q_reg_0/CLK (0.206 0.2162)
core_block_divider_regiA_q_reg_7/CLK (0.2076 0.2178)
core_block_divider_regiA_q_reg_6/CLK (0.2083 0.2185)
core_block_divider_regiA_q_reg_5/CLK (0.2066 0.2168)
core_block_divider_regiA_q_reg_4/CLK (0.2083 0.2185)
core_block_divider_regiA_q_reg_3/CLK (0.2127 0.2229)
core_block_divider_regiA_q_reg_2/CLK (0.2074 0.2176)
core_block_divider_regiA_q_reg_1/CLK (0.2109 0.2212)
core_block_divider_regiA_q_reg_0/CLK (0.2092 0.2194)