Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
8.8(ps) ~ 9.96(ps)
1
9.96(ps) ~ 11.12(ps)
3
11.12(ps) ~ 12.28(ps)
1
12.28(ps) ~ 13.44(ps)
2
13.44(ps) ~ 14.6(ps)
3
14.6(ps) ~ 15.76(ps)
6
15.76(ps) ~ 16.92(ps)
4
16.92(ps) ~ 18.08(ps)
0
18.08(ps) ~ 19.24(ps)
4
19.24(ps) ~ 20.4(ps)
4
(max, min, avg, skew) = (20.4(ps) 8.8(ps) 15.4393(ps) 11.6(ps))






Detail Phase Delay Report

TOP LEVEL:
clk (0 0)

LEVEL 1:
cellName = DFFSR
block_control_CURRENT_reg_3/CLK (0.0137 0.0137)
cellName = DFFSR
block_control_CURRENT_reg_2/CLK (0.0158 0.0158)
cellName = DFFSR
block_control_CURRENT_reg_1/CLK (0.0157 0.0157)
cellName = DFFSR
block_control_CURRENT_reg_0/CLK (0.0149 0.0149)
cellName = DFFSR
block_acc_q_reg_7/CLK (0.0111 0.0111)
cellName = DFFSR
block_acc_q_reg_6/CLK (0.0162 0.0162)
cellName = DFFSR
block_acc_q_reg_5/CLK (0.0161 0.0161)
cellName = DFFSR
block_acc_q_reg_4/CLK (0.0204 0.0204)
cellName = DFFSR
block_acc_q_reg_3/CLK (0.012 0.012)
cellName = DFFSR
block_acc_q_reg_2/CLK (0.0145 0.0145)
cellName = DFFSR
block_acc_q_reg_1/CLK (0.0088 0.0088)
cellName = DFFSR
block_acc_q_reg_0/CLK (0.0103 0.0103)
cellName = DFFSR
block_divider_regiB_q_reg_7/CLK (0.0129 0.0129)
cellName = DFFSR
block_divider_regiB_q_reg_6/CLK (0.0141 0.0141)
cellName = DFFSR
block_divider_regiB_q_reg_5/CLK (0.0153 0.0153)
cellName = DFFSR
block_divider_regiB_q_reg_4/CLK (0.0202 0.0202)
cellName = DFFSR
block_divider_regiB_q_reg_3/CLK (0.0166 0.0166)
cellName = DFFSR
block_divider_regiB_q_reg_2/CLK (0.0183 0.0183)
cellName = DFFSR
block_divider_regiB_q_reg_1/CLK (0.0188 0.0188)
cellName = DFFSR
block_divider_regiB_q_reg_0/CLK (0.0102 0.0102)
cellName = DFFSR
block_divider_regiA_q_reg_7/CLK (0.015 0.015)
cellName = DFFSR
block_divider_regiA_q_reg_6/CLK (0.0134 0.0134)
cellName = DFFSR
block_divider_regiA_q_reg_5/CLK (0.0151 0.0151)
cellName = DFFSR
block_divider_regiA_q_reg_4/CLK (0.0151 0.0151)
cellName = DFFSR
block_divider_regiA_q_reg_3/CLK (0.0198 0.0198)
cellName = DFFSR
block_divider_regiA_q_reg_2/CLK (0.019 0.019)
cellName = DFFSR
block_divider_regiA_q_reg_1/CLK (0.0202 0.0202)
cellName = DFFSR
block_divider_regiA_q_reg_0/CLK (0.0188 0.0188)