Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
8(ps) ~ 8.86(ps)
2
8.86(ps) ~ 9.72(ps)
2
9.72(ps) ~ 10.58(ps)
1
10.58(ps) ~ 11.44(ps)
2
11.44(ps) ~ 12.3(ps)
6
12.3(ps) ~ 13.16(ps)
2
13.16(ps) ~ 14.02(ps)
3
14.02(ps) ~ 14.88(ps)
2
14.88(ps) ~ 15.74(ps)
3
15.74(ps) ~ 16.6(ps)
5
(max, min, avg, skew) = (16.6(ps) 8(ps) 12.925(ps) 8.6(ps))






Detail Phase Delay Report

TOP LEVEL:
clk (0 0)

LEVEL 1:
cellName = DFFSR
block_control_CURRENT_reg_3/CLK (0.0119 0.0119)
cellName = DFFSR
block_control_CURRENT_reg_2/CLK (0.0138 0.0138)
cellName = DFFSR
block_control_CURRENT_reg_1/CLK (0.0138 0.0138)
cellName = DFFSR
block_control_CURRENT_reg_0/CLK (0.013 0.013)
cellName = DFFSR
block_acc_q_reg_7/CLK (0.0092 0.0092)
cellName = DFFSR
block_acc_q_reg_6/CLK (0.0141 0.0141)
cellName = DFFSR
block_acc_q_reg_5/CLK (0.014 0.014)
cellName = DFFSR
block_acc_q_reg_4/CLK (0.0166 0.0166)
cellName = DFFSR
block_acc_q_reg_3/CLK (0.0103 0.0103)
cellName = DFFSR
block_acc_q_reg_2/CLK (0.0121 0.0121)
cellName = DFFSR
block_acc_q_reg_1/CLK (0.008 0.008)
cellName = DFFSR
block_acc_q_reg_0/CLK (0.0084 0.0084)
cellName = DFFSR
block_divider_regiB_q_reg_7/CLK (0.0114 0.0114)
cellName = DFFSR
block_divider_regiB_q_reg_6/CLK (0.0115 0.0115)
cellName = DFFSR
block_divider_regiB_q_reg_5/CLK (0.0123 0.0123)
cellName = DFFSR
block_divider_regiB_q_reg_4/CLK (0.0166 0.0166)
cellName = DFFSR
block_divider_regiB_q_reg_3/CLK (0.0144 0.0144)
cellName = DFFSR
block_divider_regiB_q_reg_2/CLK (0.0152 0.0152)
cellName = DFFSR
block_divider_regiB_q_reg_1/CLK (0.0152 0.0152)
cellName = DFFSR
block_divider_regiB_q_reg_0/CLK (0.0092 0.0092)
cellName = DFFSR
block_divider_regiA_q_reg_7/CLK (0.0119 0.0119)
cellName = DFFSR
block_divider_regiA_q_reg_6/CLK (0.0111 0.0111)
cellName = DFFSR
block_divider_regiA_q_reg_5/CLK (0.0119 0.0119)
cellName = DFFSR
block_divider_regiA_q_reg_4/CLK (0.0121 0.0121)
cellName = DFFSR
block_divider_regiA_q_reg_3/CLK (0.0164 0.0164)
cellName = DFFSR
block_divider_regiA_q_reg_2/CLK (0.0158 0.0158)
cellName = DFFSR
block_divider_regiA_q_reg_1/CLK (0.0165 0.0165)
cellName = DFFSR
block_divider_regiA_q_reg_0/CLK (0.0152 0.0152)