Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
6.8(ps) ~ 7.8(ps)
1
7.8(ps) ~ 8.8(ps)
1
8.8(ps) ~ 9.8(ps)
3
9.8(ps) ~ 10.8(ps)
4
10.8(ps) ~ 11.8(ps)
3
11.8(ps) ~ 12.8(ps)
4
12.8(ps) ~ 13.8(ps)
2
13.8(ps) ~ 14.8(ps)
1
14.8(ps) ~ 15.8(ps)
3
15.8(ps) ~ 16.8(ps)
6
(max, min, avg, skew) = (16.8(ps) 6.8(ps) 12.55(ps) 10(ps))






Detail Phase Delay Report

TOP LEVEL:
clk (0 0)

LEVEL 1:
cellName = DFFSR
block_control_CURRENT_reg_3/CLK (0.01 0.01)
cellName = DFFSR
block_control_CURRENT_reg_2/CLK (0.0094 0.0094)
cellName = DFFSR
block_control_CURRENT_reg_1/CLK (0.0091 0.0091)
cellName = DFFSR
block_control_CURRENT_reg_0/CLK (0.0098 0.0098)
cellName = DFFSR
block_acc_q_reg_7/CLK (0.0143 0.0143)
cellName = DFFSR
block_acc_q_reg_6/CLK (0.0154 0.0154)
cellName = DFFSR
block_acc_q_reg_5/CLK (0.0154 0.0154)
cellName = DFFSR
block_acc_q_reg_4/CLK (0.0093 0.0093)
cellName = DFFSR
block_acc_q_reg_3/CLK (0.0068 0.0068)
cellName = DFFSR
block_acc_q_reg_2/CLK (0.0081 0.0081)
cellName = DFFSR
block_acc_q_reg_1/CLK (0.0102 0.0102)
cellName = DFFSR
block_acc_q_reg_0/CLK (0.0101 0.0101)
cellName = DFFSR
block_divider_regiB_q_reg_7/CLK (0.013 0.013)
cellName = DFFSR
block_divider_regiB_q_reg_6/CLK (0.0162 0.0162)
cellName = DFFSR
block_divider_regiB_q_reg_5/CLK (0.0164 0.0164)
cellName = DFFSR
block_divider_regiB_q_reg_4/CLK (0.0131 0.0131)
cellName = DFFSR
block_divider_regiB_q_reg_3/CLK (0.012 0.012)
cellName = DFFSR
block_divider_regiB_q_reg_2/CLK (0.0112 0.0112)
cellName = DFFSR
block_divider_regiB_q_reg_1/CLK (0.0121 0.0121)
cellName = DFFSR
block_divider_regiB_q_reg_0/CLK (0.0121 0.0121)
cellName = DFFSR
block_divider_regiA_q_reg_7/CLK (0.0168 0.0168)
cellName = DFFSR
block_divider_regiA_q_reg_6/CLK (0.0157 0.0157)
cellName = DFFSR
block_divider_regiA_q_reg_5/CLK (0.0168 0.0168)
cellName = DFFSR
block_divider_regiA_q_reg_4/CLK (0.0167 0.0167)
cellName = DFFSR
block_divider_regiA_q_reg_3/CLK (0.0165 0.0165)
cellName = DFFSR
block_divider_regiA_q_reg_2/CLK (0.0119 0.0119)
cellName = DFFSR
block_divider_regiA_q_reg_1/CLK (0.0113 0.0113)
cellName = DFFSR
block_divider_regiA_q_reg_0/CLK (0.0117 0.0117)