Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

SubTree from clk
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [226.1(ps) 258.9(ps)] 32.8(ps) [238.1(ps) 270.5(ps)] 32.4(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
p11/YPAD 28 [226.1(ps) 258.9(ps)] 32.8(ps) [238.1(ps) 270.5(ps)] 32.4(ps)



SubTree from p11/DI
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [226.1(ps) 258.9(ps)] 32.8(ps) [238.1(ps) 270.5(ps)] 32.4(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew


clk (0 0) load=0.450181(pf)

p11/YPAD (0.0036 0.0036)
p11/DI (0.2162 0.2283) load=0.945788(pf)

core/block_acc/q_reg[0]/CLK (0.2366 0.2485)

core/block_acc/q_reg[1]/CLK (0.2395 0.2513)

core/block_acc/q_reg[2]/CLK (0.2377 0.2496)

core/block_acc/q_reg[3]/CLK (0.2381 0.25)

core/block_acc/q_reg[4]/CLK (0.2555 0.2671)

core/block_acc/q_reg[5]/CLK (0.2576 0.2692)

core/block_acc/q_reg[6]/CLK (0.2589 0.2704)

core/block_acc/q_reg[7]/CLK (0.2354 0.2473)

core/block_divider/regiA/q_reg[7]/CLK (0.2261 0.2381)

core/block_divider/regiA/q_reg[6]/CLK (0.2513 0.2629)

core/block_divider/regiA/q_reg[5]/CLK (0.2329 0.2448)

core/block_divider/regiA/q_reg[4]/CLK (0.2531 0.2647)

core/block_divider/regiA/q_reg[3]/CLK (0.2469 0.2586)

core/block_divider/regiA/q_reg[2]/CLK (0.2414 0.2532)

core/block_divider/regiA/q_reg[1]/CLK (0.2262 0.2382)

core/block_divider/regiA/q_reg[0]/CLK (0.2366 0.2485)

core/block_control/CURRENT_reg[0]/CLK (0.2304 0.2424)

core/block_control/CURRENT_reg[1]/CLK (0.2298 0.2418)

core/block_control/CURRENT_reg[2]/CLK (0.2309 0.2429)

core/block_control/CURRENT_reg[3]/CLK (0.2307 0.2427)

core/block_divider/regiB/q_reg[7]/CLK (0.2578 0.2694)

core/block_divider/regiB/q_reg[6]/CLK (0.2583 0.2699)

core/block_divider/regiB/q_reg[5]/CLK (0.2589 0.2705)

core/block_divider/regiB/q_reg[4]/CLK (0.2575 0.269)

core/block_divider/regiB/q_reg[3]/CLK (0.2443 0.2561)

core/block_divider/regiB/q_reg[2]/CLK (0.2481 0.2598)

core/block_divider/regiB/q_reg[1]/CLK (0.2322 0.2441)

core/block_divider/regiB/q_reg[0]/CLK (0.2394 0.2513)