Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
SubTree from clk
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[319.5(ps) 336.2(ps)] |
16.7(ps) |
[319.6(ps) 336.4(ps)] |
16.8(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
p11/YPAD |
28 |
[319.5(ps) 336.2(ps)] |
16.7(ps) |
[319.6(ps) 336.4(ps)] |
16.8(ps) |
SubTree from p11/DI
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[319.5(ps) 336.2(ps)] |
16.7(ps) |
[319.6(ps) 336.4(ps)] |
16.8(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
clk (0 0) load=0.636903(pf)
p11/YPAD (0.0051 0.0051)
p11/DI (0.2882 0.2894) load=0.786606(pf)
core_block_control_CURRENT_reg_3/CLK (0.33 0.3302)
core_block_control_CURRENT_reg_2/CLK (0.3313 0.3314)
core_block_control_CURRENT_reg_1/CLK (0.3311 0.3313)
core_block_control_CURRENT_reg_0/CLK (0.3308 0.331)
core_block_acc_q_reg_7/CLK (0.3359 0.3361)
core_block_acc_q_reg_6/CLK (0.3362 0.3364)
core_block_acc_q_reg_5/CLK (0.3361 0.3363)
core_block_acc_q_reg_4/CLK (0.3356 0.3358)
core_block_acc_q_reg_3/CLK (0.3344 0.3346)
core_block_acc_q_reg_2/CLK (0.3342 0.3344)
core_block_acc_q_reg_1/CLK (0.335 0.3351)
core_block_acc_q_reg_0/CLK (0.3346 0.3348)
core_block_divider_regiB_q_reg_7/CLK (0.3311 0.3312)
core_block_divider_regiB_q_reg_6/CLK (0.3317 0.3318)
core_block_divider_regiB_q_reg_5/CLK (0.3309 0.331)
core_block_divider_regiB_q_reg_4/CLK (0.3315 0.3316)
core_block_divider_regiB_q_reg_3/CLK (0.33 0.3301)
core_block_divider_regiB_q_reg_2/CLK (0.3254 0.3255)
core_block_divider_regiB_q_reg_1/CLK (0.3228 0.3229)
core_block_divider_regiB_q_reg_0/CLK (0.3226 0.3228)
core_block_divider_regiA_q_reg_7/CLK (0.3318 0.3319)
core_block_divider_regiA_q_reg_6/CLK (0.3312 0.3313)
core_block_divider_regiA_q_reg_5/CLK (0.3313 0.3314)
core_block_divider_regiA_q_reg_4/CLK (0.3209 0.3211)
core_block_divider_regiA_q_reg_3/CLK (0.3195 0.3196)
core_block_divider_regiA_q_reg_2/CLK (0.3253 0.3254)
core_block_divider_regiA_q_reg_1/CLK (0.3232 0.3233)
core_block_divider_regiA_q_reg_0/CLK (0.3299 0.33)