Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
SubTree from clk
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[257(ps) 279.8(ps)] |
22.8(ps) |
[264.5(ps) 286.3(ps)] |
21.8(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
p11/YPAD |
28 |
[257(ps) 279.8(ps)] |
22.8(ps) |
[264.5(ps) 286.3(ps)] |
21.8(ps) |
SubTree from p11/DI
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
28 |
[257(ps) 279.8(ps)] |
22.8(ps) |
[264.5(ps) 286.3(ps)] |
21.8(ps) |
Child Tree |
Nr. Sinks |
Rise Delay |
Rise Skew |
Fall Delay |
Fall Skew |
clk (0 0) load=0.636903(pf)
p11/YPAD (0.0051 0.0051)
p11/DI (0.2401 0.2475) load=0.650126(pf)
core/block_acc/q_reg[0]/CLK (0.2738 0.2806)
core/block_acc/q_reg[1]/CLK (0.2656 0.2728)
core/block_acc/q_reg[2]/CLK (0.271 0.2778)
core/block_acc/q_reg[3]/CLK (0.2788 0.2853)
core/block_acc/q_reg[4]/CLK (0.2785 0.285)
core/block_acc/q_reg[5]/CLK (0.2788 0.2852)
core/block_acc/q_reg[6]/CLK (0.2714 0.2782)
core/block_acc/q_reg[7]/CLK (0.257 0.2645)
core/block_divider/regiA/q_reg[7]/CLK (0.277 0.2835)
core/block_divider/regiA/q_reg[6]/CLK (0.2725 0.2793)
core/block_divider/regiA/q_reg[5]/CLK (0.2754 0.282)
core/block_divider/regiA/q_reg[4]/CLK (0.2767 0.2832)
core/block_divider/regiA/q_reg[3]/CLK (0.2795 0.286)
core/block_divider/regiA/q_reg[2]/CLK (0.2797 0.2862)
core/block_divider/regiA/q_reg[1]/CLK (0.2793 0.2857)
core/block_divider/regiA/q_reg[0]/CLK (0.2798 0.2863)
core/block_control/CURRENT_reg[0]/CLK (0.2785 0.285)
core/block_control/CURRENT_reg[1]/CLK (0.2783 0.2848)
core/block_control/CURRENT_reg[2]/CLK (0.2781 0.2846)
core/block_control/CURRENT_reg[3]/CLK (0.2773 0.2838)
core/block_divider/regiB/q_reg[7]/CLK (0.2696 0.2765)
core/block_divider/regiB/q_reg[6]/CLK (0.2738 0.2805)
core/block_divider/regiB/q_reg[5]/CLK (0.2756 0.2823)
core/block_divider/regiB/q_reg[4]/CLK (0.278 0.2845)
core/block_divider/regiB/q_reg[3]/CLK (0.2782 0.2847)
core/block_divider/regiB/q_reg[2]/CLK (0.279 0.2854)
core/block_divider/regiB/q_reg[1]/CLK (0.2737 0.2804)
core/block_divider/regiB/q_reg[0]/CLK (0.2738 0.2805)