Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

SubTree from clk
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [277.1(ps) 303.6(ps)] 26.5(ps) [283.8(ps) 309.9(ps)] 26.1(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
p11/YPAD 28 [277.1(ps) 303.6(ps)] 26.5(ps) [283.8(ps) 309.9(ps)] 26.1(ps)



SubTree from p11/DI
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [277.1(ps) 303.6(ps)] 26.5(ps) [283.8(ps) 309.9(ps)] 26.1(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew


clk (0 0) load=0.636903(pf)

p11/YPAD (0.0051 0.0051)
p11/DI (0.2641 0.2713) load=0.640676(pf)

core/block_acc/q_reg[0]/CLK (0.2963 0.3027)

core/block_acc/q_reg[1]/CLK (0.2864 0.2929)

core/block_acc/q_reg[2]/CLK (0.2943 0.3007)

core/block_acc/q_reg[3]/CLK (0.3022 0.3085)

core/block_acc/q_reg[4]/CLK (0.3018 0.3082)

core/block_acc/q_reg[5]/CLK (0.3021 0.3084)

core/block_acc/q_reg[6]/CLK (0.2936 0.3)

core/block_acc/q_reg[7]/CLK (0.2771 0.2838)

core/block_divider/regiA/q_reg[7]/CLK (0.3003 0.3067)

core/block_divider/regiA/q_reg[6]/CLK (0.2956 0.3019)

core/block_divider/regiA/q_reg[5]/CLK (0.2981 0.3045)

core/block_divider/regiA/q_reg[4]/CLK (0.2992 0.3055)

core/block_divider/regiA/q_reg[3]/CLK (0.3032 0.3096)

core/block_divider/regiA/q_reg[2]/CLK (0.3035 0.3098)

core/block_divider/regiA/q_reg[1]/CLK (0.3028 0.3092)

core/block_divider/regiA/q_reg[0]/CLK (0.3036 0.3099)

core/block_control/CURRENT_reg[0]/CLK (0.3022 0.3086)

core/block_control/CURRENT_reg[1]/CLK (0.3021 0.3085)

core/block_control/CURRENT_reg[2]/CLK (0.3017 0.308)

core/block_control/CURRENT_reg[3]/CLK (0.3009 0.3072)

core/block_divider/regiB/q_reg[7]/CLK (0.2926 0.299)

core/block_divider/regiB/q_reg[6]/CLK (0.2975 0.3038)

core/block_divider/regiB/q_reg[5]/CLK (0.2995 0.3058)

core/block_divider/regiB/q_reg[4]/CLK (0.3014 0.3077)

core/block_divider/regiB/q_reg[3]/CLK (0.3014 0.3077)

core/block_divider/regiB/q_reg[2]/CLK (0.3023 0.3087)

core/block_divider/regiB/q_reg[1]/CLK (0.2974 0.3037)

core/block_divider/regiB/q_reg[0]/CLK (0.2962 0.3026)