Clock Tree clk Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

SubTree from clk
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [207.9(ps) 235.7(ps)] 27.8(ps) [218.1(ps) 246.2(ps)] 28.1(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
p11/YPAD 28 [207.9(ps) 235.7(ps)] 27.8(ps) [218.1(ps) 246.2(ps)] 28.1(ps)



SubTree from p11/DI
Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew
28 [207.9(ps) 235.7(ps)] 27.8(ps) [218.1(ps) 246.2(ps)] 28.1(ps)


Child Tree Nr. Sinks Rise Delay Rise Skew Fall Delay Fall Skew


clk (0 0) load=0.450181(pf)

p11/YPAD (0.0036 0.0036)
p11/DI (0.2012 0.2115) load=0.957989(pf)

core/block_acc/q_reg[0]/CLK (0.2189 0.2289)

core/block_acc/q_reg[1]/CLK (0.2212 0.2312)

core/block_acc/q_reg[2]/CLK (0.2204 0.2305)

core/block_acc/q_reg[3]/CLK (0.2207 0.2308)

core/block_acc/q_reg[4]/CLK (0.2317 0.2419)

core/block_acc/q_reg[5]/CLK (0.2344 0.245)

core/block_acc/q_reg[6]/CLK (0.2355 0.2461)

core/block_acc/q_reg[7]/CLK (0.2175 0.2276)

core/block_divider/regiA/q_reg[7]/CLK (0.2079 0.2181)

core/block_divider/regiA/q_reg[6]/CLK (0.2289 0.2388)

core/block_divider/regiA/q_reg[5]/CLK (0.2163 0.2264)

core/block_divider/regiA/q_reg[4]/CLK (0.2303 0.2404)

core/block_divider/regiA/q_reg[3]/CLK (0.2258 0.2358)

core/block_divider/regiA/q_reg[2]/CLK (0.2215 0.2315)

core/block_divider/regiA/q_reg[1]/CLK (0.2081 0.2183)

core/block_divider/regiA/q_reg[0]/CLK (0.2192 0.2292)

core/block_control/CURRENT_reg[0]/CLK (0.2104 0.2205)

core/block_control/CURRENT_reg[1]/CLK (0.2094 0.2196)

core/block_control/CURRENT_reg[2]/CLK (0.2108 0.2209)

core/block_control/CURRENT_reg[3]/CLK (0.2105 0.2207)

core/block_divider/regiB/q_reg[7]/CLK (0.2345 0.245)

core/block_divider/regiB/q_reg[6]/CLK (0.2352 0.2458)

core/block_divider/regiB/q_reg[5]/CLK (0.2357 0.2462)

core/block_divider/regiB/q_reg[4]/CLK (0.2344 0.2449)

core/block_divider/regiB/q_reg[3]/CLK (0.224 0.234)

core/block_divider/regiB/q_reg[2]/CLK (0.2257 0.2357)

core/block_divider/regiB/q_reg[1]/CLK (0.2162 0.2263)

core/block_divider/regiB/q_reg[0]/CLK (0.2211 0.2312)