Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
3.2(ps) ~ 4.13(ps) | 3 |
4.13(ps) ~ 5.06(ps) | 0 |
5.06(ps) ~ 5.99(ps) | 1 |
5.99(ps) ~ 6.92(ps) | 6 |
6.92(ps) ~ 7.85(ps) | 3 |
7.85(ps) ~ 8.78(ps) | 5 |
8.78(ps) ~ 9.71(ps) | 4 |
9.71(ps) ~ 10.64(ps) | 0 |
10.64(ps) ~ 11.57(ps) | 1 |
11.57(ps) ~ 12.5(ps) | 5 |
(max, min, avg, skew) = (12.5(ps) 3.2(ps) 8.21429(ps) 9.3(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = DFFSR
block_divider/regiA/q_reg[0]/CLK (0.0096 0.0096)
cellName = DFFSR
block_divider/regiA/q_reg[1]/CLK (0.0095 0.0095)
cellName = DFFSR
block_divider/regiA/q_reg[2]/CLK (0.0077 0.0077)
cellName = DFFSR
block_divider/regiA/q_reg[3]/CLK (0.0077 0.0077)
cellName = DFFSR
block_divider/regiA/q_reg[4]/CLK (0.0066 0.0066)
cellName = DFFSR
block_divider/regiA/q_reg[5]/CLK (0.0041 0.0041)
cellName = DFFSR
block_divider/regiA/q_reg[6]/CLK (0.0086 0.0086)
cellName = DFFSR
block_divider/regiA/q_reg[7]/CLK (0.012 0.012)
cellName = DFFSR
block_acc/q_reg[7]/CLK (0.0109 0.0109)
cellName = DFFSR
block_acc/q_reg[6]/CLK (0.0125 0.0125)
cellName = DFFSR
block_acc/q_reg[5]/CLK (0.012 0.012)
cellName = DFFSR
block_acc/q_reg[4]/CLK (0.0067 0.0067)
cellName = DFFSR
block_acc/q_reg[3]/CLK (0.0085 0.0085)
cellName = DFFSR
block_acc/q_reg[2]/CLK (0.0083 0.0083)
cellName = DFFSR
block_acc/q_reg[1]/CLK (0.0032 0.0032)
cellName = DFFSR
block_acc/q_reg[0]/CLK (0.0064 0.0064)
cellName = DFFSR
block_divider/regiB/q_reg[0]/CLK (0.0077 0.0077)
cellName = DFFSR
block_divider/regiB/q_reg[1]/CLK (0.0041 0.0041)
cellName = DFFSR
block_divider/regiB/q_reg[2]/CLK (0.0082 0.0082)
cellName = DFFSR
block_divider/regiB/q_reg[3]/CLK (0.0079 0.0079)
cellName = DFFSR
block_divider/regiB/q_reg[4]/CLK (0.0094 0.0094)
cellName = DFFSR
block_divider/regiB/q_reg[5]/CLK (0.0095 0.0095)
cellName = DFFSR
block_divider/regiB/q_reg[6]/CLK (0.012 0.012)
cellName = DFFSR
block_divider/regiB/q_reg[7]/CLK (0.0123 0.0123)
cellName = DFFSR
block_control/CURRENT_reg[3]/CLK (0.0064 0.0064)
cellName = DFFSR
block_control/CURRENT_reg[2]/CLK (0.0061 0.0061)
cellName = DFFSR
block_control/CURRENT_reg[1]/CLK (0.0054 0.0054)
cellName = DFFSR
block_control/CURRENT_reg[0]/CLK (0.0067 0.0067)