Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
27(ps) ~ 27.75(ps)
2
27.75(ps) ~ 28.5(ps)
0
28.5(ps) ~ 29.25(ps)
0
29.25(ps) ~ 30(ps)
2
(max, min, avg, skew) = (30(ps) 27(ps) 28.5(ps) 3(ps))

Output Delay RangeNumber of Buffer
181.5(ps) ~ 182.725(ps)
2
182.725(ps) ~ 183.95(ps)
1
183.95(ps) ~ 185.175(ps)
0
185.175(ps) ~ 186.4(ps)
1
(max, min, avg, skew) = (186.4(ps) 181.5(ps) 183.5(ps) 4.9(ps))




Level 2
Input Delay Range Number of Buffer
185.9(ps) ~ 187.99(ps)
2
187.99(ps) ~ 190.08(ps)
0
190.08(ps) ~ 192.17(ps)
1
192.17(ps) ~ 194.26(ps)
2
194.26(ps) ~ 196.35(ps)
3
196.35(ps) ~ 198.44(ps)
2
198.44(ps) ~ 200.53(ps)
2
200.53(ps) ~ 202.62(ps)
2
202.62(ps) ~ 204.71(ps)
0
204.71(ps) ~ 206.8(ps)
2
(max, min, avg, skew) = (206.8(ps) 185.9(ps) 196.806(ps) 20.9(ps))

Output Delay RangeNumber of Buffer
384.3(ps) ~ 387.08(ps)
1
387.08(ps) ~ 389.86(ps)
0
389.86(ps) ~ 392.64(ps)
4
392.64(ps) ~ 395.42(ps)
4
395.42(ps) ~ 398.2(ps)
1
398.2(ps) ~ 400.98(ps)
1
400.98(ps) ~ 403.76(ps)
1
403.76(ps) ~ 406.54(ps)
2
406.54(ps) ~ 409.32(ps)
0
409.32(ps) ~ 412.1(ps)
2
(max, min, avg, skew) = (412.1(ps) 384.3(ps) 397.556(ps) 27.8(ps))




Level 3
Input Delay Range Number of Buffer
389.9(ps) ~ 393.57(ps)
7
393.57(ps) ~ 397.24(ps)
23
397.24(ps) ~ 400.91(ps)
39
400.91(ps) ~ 404.58(ps)
45
404.58(ps) ~ 408.25(ps)
31
408.25(ps) ~ 411.92(ps)
37
411.92(ps) ~ 415.59(ps)
29
415.59(ps) ~ 419.26(ps)
26
419.26(ps) ~ 422.93(ps)
46
422.93(ps) ~ 426.6(ps)
13
(max, min, avg, skew) = (426.6(ps) 389.9(ps) 408.953(ps) 36.7(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = INVX8
clk_i__L1_I3/A (0.0275 0.0275)
clk_i__L1_I3/Y (0.1815 0.1605)

cellName = INVX8
clk_i__L1_I2/A (0.0295 0.0295)
clk_i__L1_I2/Y (0.1864 0.1651)

cellName = INVX8
clk_i__L1_I1/A (0.027 0.027)
clk_i__L1_I1/Y (0.1822 0.1611)

cellName = INVX8
clk_i__L1_I0/A (0.03 0.03)
clk_i__L1_I0/Y (0.1839 0.1629)

LEVEL 2:
cellName = INVX8
clk_i__L2_I15/A (0.1859 0.1649)
clk_i__L2_I15/Y (0.3925 0.3921)

cellName = INVX8
clk_i__L2_I14/A (0.1979 0.177)
clk_i__L2_I14/Y (0.3938 0.3945)

cellName = INVX8
clk_i__L2_I13/A (0.1962 0.1752)
clk_i__L2_I13/Y (0.3953 0.3957)

cellName = INVX8
clk_i__L2_I12/A (0.1914 0.1704)
clk_i__L2_I12/Y (0.3947 0.3947)

cellName = INVX8
clk_i__L2_I11/A (0.196 0.1747)
clk_i__L2_I11/Y (0.3916 0.3929)

cellName = INVX8
clk_i__L2_I10/A (0.2009 0.1797)
clk_i__L2_I10/Y (0.4048 0.405)

cellName = INVX8
clk_i__L2_I9/A (0.2068 0.1856)
clk_i__L2_I9/Y (0.4105 0.4108)

cellName = INVX8
clk_i__L2_I8/A (0.2057 0.1845)
clk_i__L2_I8/Y (0.4121 0.412)

cellName = INVX8
clk_i__L2_I7/A (0.1939 0.1729)
clk_i__L2_I7/Y (0.3921 0.3928)

cellName = INVX8
clk_i__L2_I6/A (0.2 0.1789)
clk_i__L2_I6/Y (0.3942 0.3954)

cellName = INVX8
clk_i__L2_I5/A (0.1951 0.174)
clk_i__L2_I5/Y (0.3995 0.3995)

cellName = INVX8
clk_i__L2_I4/A (0.1974 0.1763)
clk_i__L2_I4/Y (0.4014 0.4015)

cellName = INVX8
clk_i__L2_I3/A (0.1869 0.1659)
clk_i__L2_I3/Y (0.3843 0.3849)

cellName = INVX8
clk_i__L2_I2/A (0.2011 0.1801)
clk_i__L2_I2/Y (0.3974 0.3982)

cellName = INVX8
clk_i__L2_I1/A (0.1939 0.173)
clk_i__L2_I1/Y (0.3908 0.3914)

cellName = INVX8
clk_i__L2_I0/A (0.1998 0.1788)
clk_i__L2_I0/Y (0.4059 0.4056)

LEVEL 3:
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.3958 0.3954)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.4032 0.4028)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.3965 0.3961)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.3996 0.3992)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.4018 0.4014)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.4026 0.4021)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.4008 0.4004)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.3992 0.3988)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.3997 0.3993)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.3969 0.3965)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.397 0.3966)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.3957 0.3953)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.402 0.4016)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.4028 0.4024)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.4003 0.3999)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.3974 0.397)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.4034 0.403)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.3983 0.3979)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.4025 0.4021)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.411 0.4117)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.4044 0.4051)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.4105 0.4112)
cellName = DFFPOSX1
writew_node_reg/CLK (0.4062 0.4069)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.398 0.3987)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.4023 0.403)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.4099 0.4106)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.4027 0.4034)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.4068 0.4075)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.4054 0.4061)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.405 0.4057)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.4 0.4007)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.4065 0.4072)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.4054 0.4061)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.4085 0.4091)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.4075 0.4081)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.3997 0.4004)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.3982 0.3989)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.4022 0.4026)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.4109 0.4113)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.4127 0.4131)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.4109 0.4113)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.411 0.4114)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.4075 0.4079)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.4004 0.4008)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.4144 0.4148)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.4143 0.4147)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.4018 0.4023)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.4136 0.414)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.4 0.4004)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.3999 0.4003)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.4012 0.4016)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.4028 0.4033)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.4021 0.4025)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.4031 0.4035)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.4026 0.4031)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.4101 0.4101)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.4122 0.4122)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.4141 0.4141)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.4103 0.4103)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.406 0.406)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.4031 0.4031)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.4073 0.4073)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.4016 0.4016)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.4082 0.4082)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.4084 0.4084)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.4161 0.4161)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.4027 0.4027)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.4014 0.4014)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.4095 0.4095)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.4094 0.4094)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.4146 0.4146)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.4131 0.4131)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.4162 0.4162)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.4025 0.4025)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.3992 0.4005)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.3971 0.3984)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.4023 0.4036)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.4028 0.4041)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.3989 0.4002)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.3955 0.3968)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.396 0.3973)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.3937 0.395)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.4002 0.4015)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.4003 0.4016)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.3974 0.3987)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.398 0.3993)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.3976 0.3989)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.4018 0.4031)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.4005 0.4018)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.3945 0.3958)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.3972 0.3985)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.3959 0.3972)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.4151 0.4153)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.4212 0.4213)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.4206 0.4208)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.4209 0.4211)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.4187 0.4189)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.4167 0.4169)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.4189 0.419)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.4106 0.4108)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.4199 0.4201)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.4202 0.4204)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.4187 0.4189)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.4147 0.4149)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.412 0.4122)
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.4221 0.4222)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.4218 0.422)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.4212 0.4214)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.4155 0.4156)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.4181 0.4183)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.4223 0.4225)
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.4221 0.4223)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.4239 0.4242)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.4265 0.4268)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.4197 0.42)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.4207 0.421)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.4216 0.4219)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.4227 0.423)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.4137 0.4139)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.4208 0.4211)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.4123 0.4126)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.4184 0.4187)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.4135 0.4138)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.4232 0.4235)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.4136 0.4139)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.4253 0.4256)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.4258 0.4261)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.4266 0.4268)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.4134 0.4137)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.4235 0.4238)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.4236 0.4234)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.4216 0.4215)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.4217 0.4216)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.4207 0.4206)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.4187 0.4186)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.4216 0.4215)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.4227 0.4226)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.4198 0.4197)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.4226 0.4225)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.4233 0.4231)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.4233 0.4232)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.4217 0.4216)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.4235 0.4234)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.422 0.4219)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.4165 0.4164)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.4192 0.4191)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.4207 0.4206)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.4206 0.4205)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.4189 0.4188)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.4027 0.4034)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.402 0.4027)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.4075 0.4081)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.406 0.4066)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.3997 0.4004)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.4009 0.4016)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.4021 0.4028)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.4018 0.4025)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.3971 0.3978)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.3981 0.3988)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.403 0.4037)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.4018 0.4024)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.4056 0.4063)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.4009 0.4016)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.4017 0.4024)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.407 0.4077)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.3951 0.3958)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.4067 0.4074)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.3988 0.4)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.4069 0.408)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.4057 0.4068)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.4069 0.4081)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.4011 0.4023)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.399 0.4002)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.4028 0.404)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.4005 0.4017)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.4072 0.4083)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.4001 0.4012)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.4002 0.4014)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.3978 0.399)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.4012 0.4024)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.4003 0.4015)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.398 0.3992)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.3982 0.3994)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.4043 0.4055)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.4014 0.4027)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.4131 0.413)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.4128 0.4128)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.4119 0.4118)
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.4093 0.4092)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.4033 0.4033)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.4064 0.4064)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.4026 0.4026)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.4088 0.4088)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.4049 0.4049)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.4031 0.4031)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.4155 0.4155)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.4156 0.4156)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.4131 0.4131)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.4102 0.4102)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.4099 0.4099)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.4093 0.4093)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.4075 0.4075)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.4147 0.4147)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.4034 0.4034)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.42 0.4201)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.4098 0.41)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.4098 0.4099)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.4199 0.42)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.4111 0.4112)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.4109 0.411)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.411 0.4111)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.4198 0.4199)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.4094 0.4095)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.418 0.4181)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.4109 0.411)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.411 0.4111)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.42 0.4201)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.4165 0.4166)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.419 0.4191)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.4073 0.4074)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.4102 0.4103)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.4132 0.4133)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.4085 0.4086)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.3991 0.3997)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.398 0.3986)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.3994 0.4)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.3917 0.3923)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.3926 0.3932)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.3966 0.3972)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.3945 0.3951)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.3965 0.3971)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.3973 0.3979)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.3969 0.3975)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.397 0.3975)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.3957 0.3963)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.3922 0.3928)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.3912 0.3918)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.3899 0.3905)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.3926 0.3932)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.3932 0.3938)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.3947 0.3953)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.4079 0.4086)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.4086 0.4093)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.4124 0.4132)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.4115 0.4122)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.4015 0.4023)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.41 0.4108)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.4058 0.4066)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.4036 0.4044)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.4082 0.409)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.4088 0.4096)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.4123 0.4131)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.4061 0.4069)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.4087 0.4094)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.4117 0.4124)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.4056 0.4064)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.406 0.4067)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.4023 0.4031)
cellName = DFFPOSX1
int_node_reg/CLK (0.4093 0.4101)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.4188 0.4194)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.4149 0.4155)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.4164 0.417)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.4185 0.4191)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.4104 0.411)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.406 0.4066)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.4227 0.4233)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.4179 0.4185)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.4229 0.4235)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.4201 0.4207)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.4227 0.4233)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.422 0.4226)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.4176 0.4182)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.3951 0.3957)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.4204 0.421)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.4012 0.4018)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.4228 0.4234)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.3955 0.3961)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.4167 0.4164)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.4199 0.4195)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.4176 0.4173)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.414 0.4137)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.4229 0.4226)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.4209 0.4206)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.4195 0.4191)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.4199 0.4196)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.4133 0.413)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.4235 0.4232)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.4217 0.4214)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.4211 0.4208)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.4205 0.4202)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.4181 0.4178)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.4234 0.4231)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.4191 0.4188)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.4195 0.4192)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.4127 0.4124)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.4189 0.4186)