Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
1.5(ps) ~ 1.5(ps) | 1 |
(max, min, avg, skew) = (1.5(ps) 1.5(ps) 1.5(ps) 0(ps))
Output Delay Range | Number of Buffer |
182.8(ps) ~ 182.8(ps) | 1 |
(max, min, avg, skew) = (182.8(ps) 182.8(ps) 182.8(ps) 0(ps))
Level 2
Input Delay Range |
Number of Buffer |
196.4(ps) ~ 197.025(ps) | 1 |
197.025(ps) ~ 197.65(ps) | 0 |
197.65(ps) ~ 198.275(ps) | 2 |
198.275(ps) ~ 198.9(ps) | 1 |
(max, min, avg, skew) = (198.9(ps) 196.4(ps) 197.85(ps) 2.5(ps))
Output Delay Range | Number of Buffer |
385.3(ps) ~ 387.85(ps) | 1 |
387.85(ps) ~ 390.4(ps) | 1 |
390.4(ps) ~ 392.95(ps) | 1 |
392.95(ps) ~ 395.5(ps) | 1 |
(max, min, avg, skew) = (395.5(ps) 385.3(ps) 390.875(ps) 10.2(ps))
Level 3
Input Delay Range |
Number of Buffer |
390(ps) ~ 391.11(ps) | 5 |
391.11(ps) ~ 392.22(ps) | 2 |
392.22(ps) ~ 393.33(ps) | 0 |
393.33(ps) ~ 394.44(ps) | 0 |
394.44(ps) ~ 395.55(ps) | 2 |
395.55(ps) ~ 396.66(ps) | 2 |
396.66(ps) ~ 397.77(ps) | 2 |
397.77(ps) ~ 398.88(ps) | 4 |
398.88(ps) ~ 399.99(ps) | 6 |
399.99(ps) ~ 401.1(ps) | 5 |
(max, min, avg, skew) = (401.1(ps) 390(ps) 396.546(ps) 11.1(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = INVX8
clk__L1_I0/A (0.0015 0.0015)
clk__L1_I0/Y (0.1828 0.1945)
LEVEL 2:
cellName = INVX8
clk__L2_I3/A (0.1981 0.2097)
clk__L2_I3/Y (0.3853 0.3663)
cellName = INVX8
clk__L2_I2/A (0.1989 0.2106)
clk__L2_I2/Y (0.3901 0.3715)
cellName = INVX8
clk__L2_I1/A (0.1964 0.2081)
clk__L2_I1/Y (0.3926 0.3746)
cellName = INVX8
clk__L2_I0/A (0.198 0.2096)
clk__L2_I0/Y (0.3955 0.3778)
LEVEL 3:
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.3901 0.3711)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.3904 0.3714)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.39 0.371)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.3909 0.3719)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.391 0.372)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.3917 0.3727)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.3918 0.3728)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.3948 0.3762)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.3958 0.3772)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.3949 0.3763)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.3959 0.3773)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.3981 0.3795)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.3981 0.3795)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.3986 0.38)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.3976 0.3796)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.3977 0.3797)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.3989 0.3809)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.3978 0.3798)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.4004 0.3824)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.4009 0.3829)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.4011 0.3831)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.3991 0.3814)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.3992 0.3815)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.3994 0.3817)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.3993 0.3816)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.3994 0.3817)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.4002 0.3825)
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.4002 0.3825)