Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
19.4(ps) ~ 20.68(ps) | 1 |
20.68(ps) ~ 21.96(ps) | 0 |
21.96(ps) ~ 23.24(ps) | 5 |
23.24(ps) ~ 24.52(ps) | 3 |
24.52(ps) ~ 25.8(ps) | 2 |
25.8(ps) ~ 27.08(ps) | 4 |
27.08(ps) ~ 28.36(ps) | 2 |
28.36(ps) ~ 29.64(ps) | 5 |
29.64(ps) ~ 30.92(ps) | 2 |
30.92(ps) ~ 32.2(ps) | 4 |
(max, min, avg, skew) = (32.2(ps) 19.4(ps) 26.7393(ps) 12.8(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.0225 0.0225)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.0289 0.0289)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.0194 0.0194)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.0222 0.0222)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.0247 0.0247)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.0229 0.0229)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.0224 0.0224)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.0229 0.0229)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.0259 0.0259)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.0269 0.0269)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.0271 0.0271)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.0266 0.0266)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.0252 0.0252)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.0241 0.0241)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.029 0.029)
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.0317 0.0317)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.0307 0.0307)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.0286 0.0286)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.0291 0.0291)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.0311 0.0311)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.0284 0.0284)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.0282 0.0282)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.0266 0.0266)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.0242 0.0242)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.0242 0.0242)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.0322 0.0322)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.0309 0.0309)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.0321 0.0321)