Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
10.9(ps) ~ 10.95(ps)
1
10.95(ps) ~ 11(ps)
1
(max, min, avg, skew) = (11(ps) 10.9(ps) 10.95(ps) 0.1(ps))

Output Delay RangeNumber of Buffer
156.6(ps) ~ 162.25(ps)
1
162.25(ps) ~ 167.9(ps)
1
(max, min, avg, skew) = (167.9(ps) 156.6(ps) 162.25(ps) 11.3(ps))




Level 2
Input Delay Range Number of Buffer
170.4(ps) ~ 172.5(ps)
1
172.5(ps) ~ 174.6(ps)
0
174.6(ps) ~ 176.7(ps)
1
176.7(ps) ~ 178.8(ps)
0
178.8(ps) ~ 180.9(ps)
2
180.9(ps) ~ 183(ps)
3
183(ps) ~ 185.1(ps)
0
185.1(ps) ~ 187.2(ps)
3
187.2(ps) ~ 189.3(ps)
0
189.3(ps) ~ 191.4(ps)
2
(max, min, avg, skew) = (191.4(ps) 170.4(ps) 182.458(ps) 21(ps))

Output Delay RangeNumber of Buffer
388.2(ps) ~ 391.44(ps)
1
391.44(ps) ~ 394.68(ps)
0
394.68(ps) ~ 397.92(ps)
0
397.92(ps) ~ 401.16(ps)
0
401.16(ps) ~ 404.4(ps)
5
404.4(ps) ~ 407.64(ps)
0
407.64(ps) ~ 410.88(ps)
4
410.88(ps) ~ 414.12(ps)
0
414.12(ps) ~ 417.36(ps)
1
417.36(ps) ~ 420.6(ps)
1
(max, min, avg, skew) = (420.6(ps) 388.2(ps) 406.558(ps) 32.4(ps))




Level 3
Input Delay Range Number of Buffer
392.2(ps) ~ 397.65(ps)
11
397.65(ps) ~ 403.1(ps)
9
403.1(ps) ~ 408.55(ps)
16
408.55(ps) ~ 414(ps)
36
414(ps) ~ 419.45(ps)
108
419.45(ps) ~ 424.9(ps)
51
424.9(ps) ~ 430.35(ps)
40
430.35(ps) ~ 435.8(ps)
11
435.8(ps) ~ 441.25(ps)
4
441.25(ps) ~ 446.7(ps)
10
(max, min, avg, skew) = (446.7(ps) 392.2(ps) 418.631(ps) 54.5(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = INVX8
clk_i__L1_I1/A (0.0109 0.0109)
clk_i__L1_I1/Y (0.1566 0.1388)

cellName = INVX8
clk_i__L1_I0/A (0.011 0.011)
clk_i__L1_I0/Y (0.1679 0.1502)

LEVEL 2:
cellName = INVX8
clk_i__L2_I11/A (0.1704 0.1525)
clk_i__L2_I11/Y (0.3882 0.3819)

cellName = INVX8
clk_i__L2_I10/A (0.1806 0.1634)
clk_i__L2_I10/Y (0.4018 0.3946)

cellName = INVX8
clk_i__L2_I9/A (0.181 0.1638)
clk_i__L2_I9/Y (0.4036 0.3963)

cellName = INVX8
clk_i__L2_I8/A (0.1854 0.1687)
clk_i__L2_I8/Y (0.4093 0.4014)

cellName = INVX8
clk_i__L2_I7/A (0.1854 0.1686)
clk_i__L2_I7/Y (0.4084 0.4007)

cellName = INVX8
clk_i__L2_I6/A (0.1823 0.1653)
clk_i__L2_I6/Y (0.4042 0.3968)

cellName = INVX8
clk_i__L2_I5/A (0.1795 0.1625)
clk_i__L2_I5/Y (0.4024 0.3943)

cellName = INVX8
clk_i__L2_I4/A (0.1861 0.1696)
clk_i__L2_I4/Y (0.4093 0.4006)

cellName = INVX8
clk_i__L2_I3/A (0.1764 0.1591)
clk_i__L2_I3/Y (0.4039 0.3957)

cellName = INVX8
clk_i__L2_I2/A (0.1812 0.1643)
clk_i__L2_I2/Y (0.4105 0.4018)

cellName = INVX8
clk_i__L2_I1/A (0.1914 0.1751)
clk_i__L2_I1/Y (0.4165 0.4074)

cellName = INVX8
clk_i__L2_I0/A (0.1898 0.1735)
clk_i__L2_I0/Y (0.4206 0.3975)

LEVEL 3:
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.3974 0.3911)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.4028 0.3965)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.4051 0.3988)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.4016 0.3953)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.3977 0.3914)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.3924 0.3861)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.4054 0.3991)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.3924 0.3861)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.3922 0.3859)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.4009 0.3946)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.4011 0.3948)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.4014 0.3951)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.4002 0.3939)
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.4012 0.3949)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.4034 0.3971)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.4016 0.3953)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.4056 0.3992)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.3941 0.3877)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.3951 0.3888)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.3955 0.3892)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.3956 0.3893)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.3967 0.3904)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.3974 0.3911)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.3957 0.3894)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.408 0.4008)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.4078 0.4006)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.4114 0.4042)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.413 0.4058)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.411 0.4038)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.4113 0.4041)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.4062 0.399)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.4087 0.4015)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.4061 0.3989)
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.4088 0.4016)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.4082 0.401)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.4142 0.4069)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.4062 0.399)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.4133 0.4061)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.4118 0.4046)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.4135 0.4063)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.4132 0.406)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.4074 0.4002)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.4073 0.4001)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.4141 0.4069)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.4136 0.4064)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.4092 0.402)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.4091 0.4019)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.4092 0.402)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.4078 0.4006)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.4175 0.4102)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.417 0.4097)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.4171 0.4098)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.4169 0.4096)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.4167 0.4094)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.4173 0.41)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.4233 0.416)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.4175 0.4102)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.4158 0.4085)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.4168 0.4095)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.4238 0.4165)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.4158 0.4085)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.416 0.4087)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.4152 0.4079)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.4246 0.4173)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.4242 0.4169)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.4244 0.4171)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.416 0.4087)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.4162 0.4089)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.4155 0.4082)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.4157 0.4084)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.4167 0.4094)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.4199 0.4126)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.4221 0.4148)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.4187 0.4114)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.4198 0.4119)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.4184 0.4105)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.4136 0.4057)
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.4196 0.4117)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.4199 0.4119)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.4175 0.4096)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.4199 0.412)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.4219 0.414)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.4168 0.4089)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.4169 0.409)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.4206 0.4126)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.4225 0.4146)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.4215 0.4136)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.4223 0.4144)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.4217 0.4138)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.4228 0.4149)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.4228 0.4149)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.4185 0.4106)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.4225 0.4146)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.4153 0.4074)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.415 0.4071)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.4149 0.407)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.4169 0.409)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.4162 0.4083)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.4165 0.4086)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.4173 0.4096)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.4184 0.4107)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.4176 0.4099)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.4175 0.4098)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.4191 0.4113)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.4192 0.4115)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.4166 0.4089)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.4212 0.4135)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.4168 0.4091)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.4161 0.4084)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.4178 0.4101)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.4238 0.4161)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.4184 0.4106)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.4182 0.4105)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.4263 0.4186)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.4257 0.418)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.4253 0.4176)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.4264 0.4187)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.4229 0.4152)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.4216 0.4139)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.4216 0.4139)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.4216 0.4139)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.4217 0.4139)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.4205 0.4128)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.418 0.4103)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.4133 0.4059)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.4167 0.4092)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.4166 0.4092)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.416 0.4085)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.4085 0.401)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.4103 0.4029)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.4107 0.4033)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.4094 0.402)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.4131 0.4057)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.4148 0.4074)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.4128 0.4054)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.4137 0.4063)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.4185 0.4111)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.4161 0.4087)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.4166 0.4092)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.4175 0.4101)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.4185 0.4111)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.4175 0.4101)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.4161 0.4087)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.4123 0.4049)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.4132 0.4058)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.4169 0.4095)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.417 0.4095)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.4174 0.41)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.4182 0.4108)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.4203 0.4122)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.4202 0.4121)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.4122 0.4041)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.4096 0.4015)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.4149 0.4068)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.4089 0.4008)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.4116 0.4035)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.409 0.4009)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.4192 0.4111)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.4132 0.405)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.4191 0.411)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.4165 0.4083)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.4076 0.3995)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.4111 0.403)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.4142 0.4061)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.4077 0.3996)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.4104 0.4023)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.414 0.4059)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.4165 0.4083)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.4169 0.4088)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.417 0.4089)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.4172 0.4091)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.4181 0.41)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.4194 0.4113)
cellName = DFFPOSX1
writew_node_reg/CLK (0.4171 0.4084)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.422 0.4133)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.4244 0.4156)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.4183 0.4096)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.4177 0.409)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.4159 0.4072)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.4242 0.4155)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.4185 0.4098)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.4164 0.4077)
cellName = DFFPOSX1
int_node_reg/CLK (0.4174 0.4087)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.4226 0.4139)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.4198 0.4111)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.4154 0.4067)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.4123 0.4036)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.415 0.4063)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.4184 0.4096)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.4171 0.4084)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.4139 0.4052)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.4177 0.409)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.4169 0.4082)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.4168 0.4081)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.4167 0.408)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.4248 0.4161)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.4247 0.416)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.4169 0.4087)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.419 0.4108)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.415 0.4068)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.4195 0.4113)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.4191 0.4109)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.4192 0.4109)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.4191 0.4109)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.4192 0.411)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.4185 0.4102)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.4175 0.4093)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.4191 0.4109)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.419 0.4107)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.4191 0.4109)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.4203 0.4121)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.4185 0.4103)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.4205 0.4123)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.421 0.4128)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.421 0.4128)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.4137 0.4055)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.412 0.4038)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.4188 0.4106)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.4194 0.4112)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.4193 0.4111)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.4191 0.4109)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.4172 0.409)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.425 0.4162)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.426 0.4173)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.4246 0.4159)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.4285 0.4197)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.4208 0.4121)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.4204 0.4117)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.4214 0.4127)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.421 0.4123)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.4189 0.4102)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.4286 0.4198)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.4244 0.4157)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.4278 0.4191)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.4258 0.4171)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.424 0.4153)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.425 0.4163)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.4218 0.4131)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.4271 0.4184)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.428 0.4193)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.418 0.4093)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.4273 0.4185)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.4273 0.4186)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.418 0.4093)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.4205 0.4118)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.4192 0.4105)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.4258 0.4171)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.4294 0.4203)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.4289 0.4198)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.4293 0.4202)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.4298 0.4206)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.4258 0.4167)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.4282 0.4191)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.4277 0.4186)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.4259 0.4168)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.4249 0.4158)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.4289 0.4198)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.4291 0.42)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.427 0.4179)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.4265 0.4174)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.4278 0.4187)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.4274 0.4183)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.4277 0.4186)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.4274 0.4183)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.4279 0.4187)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.4272 0.4181)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.4257 0.4166)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.4263 0.4172)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.4267 0.4175)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.429 0.4199)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.4273 0.4182)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.4437 0.4205)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.4459 0.4228)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.4429 0.4197)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.4445 0.4213)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.4456 0.4224)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.4452 0.422)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.445 0.4218)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.4381 0.4148)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.4358 0.4125)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.4341 0.4109)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.4354 0.4122)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.4332 0.4099)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.4328 0.4096)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.4347 0.4114)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.4465 0.4234)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.4467 0.4236)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.4328 0.4095)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.4335 0.4103)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.4361 0.4128)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.4338 0.4105)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.4341 0.4109)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.4337 0.4105)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.4352 0.4119)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.4361 0.4129)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.4433 0.4201)