Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
1.7(ps) ~ 1.7(ps) | 1 |
(max, min, avg, skew) = (1.7(ps) 1.7(ps) 1.7(ps) 0(ps))
Output Delay Range | Number of Buffer |
102.5(ps) ~ 102.5(ps) | 1 |
(max, min, avg, skew) = (102.5(ps) 102.5(ps) 102.5(ps) 0(ps))
Level 2
Input Delay Range |
Number of Buffer |
109.9(ps) ~ 110.55(ps) | 1 |
110.55(ps) ~ 111.2(ps) | 1 |
(max, min, avg, skew) = (111.2(ps) 109.9(ps) 110.55(ps) 1.3(ps))
Output Delay Range | Number of Buffer |
254.7(ps) ~ 259.45(ps) | 1 |
259.45(ps) ~ 264.2(ps) | 1 |
(max, min, avg, skew) = (264.2(ps) 254.7(ps) 259.45(ps) 9.5(ps))
Level 3
Input Delay Range |
Number of Buffer |
261.3(ps) ~ 262.94(ps) | 1 |
262.94(ps) ~ 264.58(ps) | 2 |
264.58(ps) ~ 266.22(ps) | 0 |
266.22(ps) ~ 267.86(ps) | 2 |
267.86(ps) ~ 269.5(ps) | 1 |
269.5(ps) ~ 271.14(ps) | 4 |
271.14(ps) ~ 272.78(ps) | 2 |
272.78(ps) ~ 274.42(ps) | 4 |
274.42(ps) ~ 276.06(ps) | 9 |
276.06(ps) ~ 277.7(ps) | 3 |
(max, min, avg, skew) = (277.7(ps) 261.3(ps) 272.111(ps) 16.4(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = INVX8
clk__L1_I0/A (0.0017 0.0017)
clk__L1_I0/Y (0.1025 0.0816)
LEVEL 2:
cellName = INVX8
clk__L2_I1/A (0.1112 0.09)
clk__L2_I1/Y (0.2642 0.2624)
cellName = INVX8
clk__L2_I0/A (0.1099 0.0888)
clk__L2_I0/Y (0.2547 0.251)
LEVEL 3:
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.2749 0.2731)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.2696 0.2678)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.2755 0.2737)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.2703 0.2685)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.272 0.2702)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.2695 0.2676)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.2733 0.2715)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.2744 0.2726)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.2739 0.272)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.275 0.2732)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.2746 0.2728)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.2751 0.2733)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.2756 0.2738)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.2702 0.2684)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.2771 0.274)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.2665 0.2636)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.2749 0.2718)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.2725 0.2695)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.2752 0.2721)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.2756 0.2725)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.2731 0.27)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.2674 0.2644)
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.2694 0.2664)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.2633 0.2602)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.2639 0.2608)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.2773 0.2742)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.2613 0.2581)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.2777 0.2746)