Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
1.8(ps) ~ 1.8(ps) | 1 |
(max, min, avg, skew) = (1.8(ps) 1.8(ps) 1.8(ps) 0(ps))
Output Delay Range | Number of Buffer |
102.3(ps) ~ 102.3(ps) | 1 |
(max, min, avg, skew) = (102.3(ps) 102.3(ps) 102.3(ps) 0(ps))
Level 2
Input Delay Range |
Number of Buffer |
106.7(ps) ~ 107.5(ps) | 1 |
107.5(ps) ~ 108.3(ps) | 1 |
(max, min, avg, skew) = (108.3(ps) 106.7(ps) 107.5(ps) 1.6(ps))
Output Delay Range | Number of Buffer |
260.5(ps) ~ 260.9(ps) | 1 |
260.9(ps) ~ 261.3(ps) | 1 |
(max, min, avg, skew) = (261.3(ps) 260.5(ps) 260.9(ps) 0.8(ps))
Level 3
Input Delay Range |
Number of Buffer |
263.2(ps) ~ 265.49(ps) | 2 |
265.49(ps) ~ 267.78(ps) | 6 |
267.78(ps) ~ 270.07(ps) | 2 |
270.07(ps) ~ 272.36(ps) | 3 |
272.36(ps) ~ 274.65(ps) | 7 |
274.65(ps) ~ 276.94(ps) | 0 |
276.94(ps) ~ 279.23(ps) | 1 |
279.23(ps) ~ 281.52(ps) | 2 |
281.52(ps) ~ 283.81(ps) | 2 |
283.81(ps) ~ 286.1(ps) | 3 |
(max, min, avg, skew) = (286.1(ps) 263.2(ps) 273.368(ps) 22.9(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = INVX8
clk__L1_I0/A (0.0018 0.0018)
clk__L1_I0/Y (0.1023 0.0861)
LEVEL 2:
cellName = INVX8
clk__L2_I1/A (0.1083 0.0921)
clk__L2_I1/Y (0.2605 0.2589)
cellName = INVX8
clk__L2_I0/A (0.1067 0.0904)
clk__L2_I0/Y (0.2613 0.2594)
LEVEL 3:
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.2719 0.2703)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.2662 0.2646)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.2727 0.271)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.2673 0.2657)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.2671 0.2655)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.2657 0.2641)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.2699 0.2683)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.2727 0.2711)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.2708 0.2692)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.2736 0.272)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.2738 0.2722)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.2744 0.2727)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.2731 0.2715)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.2669 0.2653)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.2851 0.2832)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.2683 0.2664)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.2815 0.2796)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.2779 0.276)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.2823 0.2804)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.2834 0.2815)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.2794 0.2775)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.271 0.2691)
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.2734 0.2715)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.265 0.2631)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.2656 0.2637)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.2861 0.2843)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.2632 0.2613)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.286 0.2841)