Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
12.3(ps) ~ 14.91(ps) | 1 |
14.91(ps) ~ 17.52(ps) | 5 |
17.52(ps) ~ 20.13(ps) | 3 |
20.13(ps) ~ 22.74(ps) | 0 |
22.74(ps) ~ 25.35(ps) | 0 |
25.35(ps) ~ 27.96(ps) | 0 |
27.96(ps) ~ 30.57(ps) | 3 |
30.57(ps) ~ 33.18(ps) | 9 |
33.18(ps) ~ 35.79(ps) | 2 |
35.79(ps) ~ 38.4(ps) | 5 |
(max, min, avg, skew) = (38.4(ps) 12.3(ps) 27.9321(ps) 26.1(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.0315 0.0315)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.0317 0.0317)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.0376 0.0376)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.0196 0.0196)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.0185 0.0185)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.0158 0.0158)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.0191 0.0191)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.0173 0.0173)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.0156 0.0156)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.0123 0.0123)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.0153 0.0153)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.0151 0.0151)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.0318 0.0318)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.0321 0.0321)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.0383 0.0383)
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.0365 0.0365)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.0384 0.0384)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.0314 0.0314)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.0381 0.0381)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.0302 0.0302)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.0354 0.0354)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.031 0.031)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.0306 0.0306)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.035 0.035)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.0328 0.0328)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.0295 0.0295)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.0312 0.0312)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.0304 0.0304)