Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
1.7(ps) ~ 1.7(ps)
1
(max, min, avg, skew) = (1.7(ps) 1.7(ps) 1.7(ps) 0(ps))

Output Delay RangeNumber of Buffer
374.3(ps) ~ 374.3(ps)
1
(max, min, avg, skew) = (374.3(ps) 374.3(ps) 374.3(ps) 0(ps))




Level 2
Input Delay Range Number of Buffer
377.2(ps) ~ 378.1(ps)
1
378.1(ps) ~ 379(ps)
0
379(ps) ~ 379.9(ps)
2
(max, min, avg, skew) = (379.9(ps) 377.2(ps) 378.867(ps) 2.7(ps))

Output Delay RangeNumber of Buffer
668.2(ps) ~ 670.833(ps)
2
670.833(ps) ~ 673.467(ps)
0
673.467(ps) ~ 676.1(ps)
1
(max, min, avg, skew) = (676.1(ps) 668.2(ps) 670.9(ps) 7.9(ps))




Level 3
Input Delay Range Number of Buffer
677.6(ps) ~ 680.18(ps)
2
680.18(ps) ~ 682.76(ps)
3
682.76(ps) ~ 685.34(ps)
5
685.34(ps) ~ 687.92(ps)
2
687.92(ps) ~ 690.5(ps)
1
690.5(ps) ~ 693.08(ps)
0
693.08(ps) ~ 695.66(ps)
1
695.66(ps) ~ 698.24(ps)
1
698.24(ps) ~ 700.82(ps)
1
700.82(ps) ~ 703.4(ps)
2
(max, min, avg, skew) = (703.4(ps) 677.6(ps) 687.961(ps) 25.8(ps))

Output Delay RangeNumber of Buffer
929(ps) ~ 933.49(ps)
2
933.49(ps) ~ 937.98(ps)
4
937.98(ps) ~ 942.47(ps)
0
942.47(ps) ~ 946.96(ps)
4
946.96(ps) ~ 951.45(ps)
3
951.45(ps) ~ 955.94(ps)
2
955.94(ps) ~ 960.43(ps)
1
960.43(ps) ~ 964.92(ps)
0
964.92(ps) ~ 969.41(ps)
1
969.41(ps) ~ 973.9(ps)
1
(max, min, avg, skew) = (973.9(ps) 929(ps) 946.222(ps) 44.9(ps))




Level 4
Input Delay Range Number of Buffer
935(ps) ~ 940.56(ps)
23
940.56(ps) ~ 946.12(ps)
27
946.12(ps) ~ 951.68(ps)
35
951.68(ps) ~ 957.24(ps)
62
957.24(ps) ~ 962.8(ps)
57
962.8(ps) ~ 968.36(ps)
43
968.36(ps) ~ 973.92(ps)
15
973.92(ps) ~ 979.48(ps)
7
979.48(ps) ~ 985.04(ps)
8
985.04(ps) ~ 990.6(ps)
19
(max, min, avg, skew) = (990.6(ps) 935(ps) 958.256(ps) 55.6(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = CLKBUF1
clk_i__L1_I0/A (0.0017 0.0017)
clk_i__L1_I0/Y (0.3743 0.373)

LEVEL 2:
cellName = INVX8
clk_i__L2_I2/A (0.3772 0.3759)
clk_i__L2_I2/Y (0.6684 0.6367)

cellName = INVX8
clk_i__L2_I1/A (0.3799 0.3786)
clk_i__L2_I1/Y (0.6682 0.6368)

cellName = INVX8
clk_i__L2_I0/A (0.3795 0.3782)
clk_i__L2_I0/Y (0.6761 0.644)

LEVEL 3:
cellName = INVX8
clk_i__L3_I17/A (0.6844 0.6527)
clk_i__L3_I17/Y (0.9341 0.9329)

cellName = INVX8
clk_i__L3_I16/A (0.6813 0.6496)
clk_i__L3_I16/Y (0.9363 0.9347)

cellName = INVX8
clk_i__L3_I15/A (0.6798 0.6481)
clk_i__L3_I15/Y (0.9339 0.9189)

cellName = INVX8
clk_i__L3_I14/A (0.6848 0.6531)
clk_i__L3_I14/Y (0.9458 0.9437)

cellName = INVX8
clk_i__L3_I13/A (0.682 0.6503)
clk_i__L3_I13/Y (0.946 0.9436)

cellName = INVX8
clk_i__L3_I12/A (0.6855 0.6538)
clk_i__L3_I12/Y (0.9488 0.9465)

cellName = INVX8
clk_i__L3_I11/A (0.6822 0.6508)
clk_i__L3_I11/Y (0.9315 0.9303)

cellName = INVX8
clk_i__L3_I10/A (0.6776 0.6462)
clk_i__L3_I10/Y (0.929 0.9276)

cellName = INVX8
clk_i__L3_I9/A (0.6845 0.6531)
clk_i__L3_I9/Y (0.9358 0.9345)

cellName = INVX8
clk_i__L3_I8/A (0.6848 0.6534)
clk_i__L3_I8/Y (0.9427 0.9408)

cellName = INVX8
clk_i__L3_I7/A (0.6868 0.6554)
clk_i__L3_I7/Y (0.9474 0.9452)

cellName = INVX8
clk_i__L3_I6/A (0.6851 0.6537)
clk_i__L3_I6/Y (0.9456 0.9435)

cellName = INVX8
clk_i__L3_I5/A (0.6962 0.6641)
clk_i__L3_I5/Y (0.9475 0.9463)

cellName = INVX8
clk_i__L3_I4/A (0.6994 0.6673)
clk_i__L3_I4/Y (0.9544 0.9528)

cellName = INVX8
clk_i__L3_I3/A (0.6889 0.6568)
clk_i__L3_I3/Y (0.9546 0.9522)

cellName = INVX8
clk_i__L3_I2/A (0.6953 0.6632)
clk_i__L3_I2/Y (0.9584 0.9562)

cellName = INVX8
clk_i__L3_I1/A (0.7034 0.6713)
clk_i__L3_I1/Y (0.9663 0.9641)

cellName = INVX8
clk_i__L3_I0/A (0.7013 0.6691)
clk_i__L3_I0/Y (0.9739 0.971)

LEVEL 4:
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.9446 0.9434)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.943 0.9418)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.9431 0.9419)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.9426 0.9414)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.9443 0.9431)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.9437 0.9425)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.9433 0.9421)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.9452 0.944)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.9453 0.9441)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.9452 0.944)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.9447 0.9435)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.9425 0.9413)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.9409 0.9397)
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.94 0.9388)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.9425 0.9413)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.9387 0.9375)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.9517 0.9501)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.9447 0.9431)
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.951 0.9494)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.9448 0.9432)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.9527 0.9511)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.9524 0.9507)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.9508 0.9492)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.9513 0.9497)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.9483 0.9467)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.944 0.9424)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.9534 0.9518)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.9492 0.9476)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.9441 0.9424)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.9503 0.9487)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.949 0.9474)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.9513 0.9497)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.9603 0.9453)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.9524 0.9373)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.9554 0.9403)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.9581 0.943)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.9543 0.9392)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.9565 0.9414)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.9542 0.9391)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.9592 0.9441)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.9535 0.9384)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.9597 0.9446)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.9556 0.9405)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.9488 0.9337)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.9558 0.9408)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.9493 0.9341)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.96 0.945)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.9498 0.9347)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.9538 0.9517)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.9542 0.9521)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.9545 0.9524)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.9563 0.9542)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.958 0.9558)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.9575 0.9554)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.9589 0.9568)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.9591 0.957)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.9537 0.9516)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.9541 0.952)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.9582 0.9561)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.9587 0.9566)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.9598 0.9577)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.9575 0.9554)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.9597 0.9576)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.9579 0.9558)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.954 0.9519)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.9522 0.9498)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.9571 0.9547)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.955 0.9526)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.955 0.9526)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.9594 0.957)
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.9562 0.9538)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.955 0.9526)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.96 0.9575)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.9527 0.9503)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.9522 0.9498)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.9526 0.9502)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.9536 0.9512)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.955 0.9526)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.9583 0.9559)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.9537 0.9513)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.952 0.9496)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.9522 0.9498)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.9588 0.9565)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.9602 0.9579)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.9571 0.9548)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.9588 0.9565)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.9568 0.9545)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.9579 0.9556)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.9577 0.9554)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.9582 0.9559)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.9581 0.9557)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.9607 0.9584)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.9629 0.9606)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.9628 0.9605)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.9588 0.9565)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.9607 0.9584)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.9612 0.9589)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.9612 0.9588)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.9622 0.9599)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.9402 0.939)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.935 0.9338)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.9381 0.9369)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.9407 0.9395)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.9402 0.939)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.9379 0.9367)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.9391 0.9379)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.9353 0.9341)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.9354 0.9342)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.9374 0.9362)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.9387 0.9375)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.9355 0.9343)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.9377 0.9365)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.9401 0.9389)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.9386 0.9374)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.94 0.9388)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.9387 0.9373)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.9485 0.9471)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.9495 0.9481)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.9393 0.9378)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.9383 0.9369)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.9387 0.9373)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.9382 0.9368)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.9392 0.9378)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.9472 0.9458)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.9463 0.9449)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.9448 0.9434)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.9434 0.942)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.9439 0.9425)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.9457 0.9442)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.9412 0.9398)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.949 0.9476)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.9467 0.9454)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.954 0.9527)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.9531 0.9518)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.9535 0.9522)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.9529 0.9516)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.9508 0.9495)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.9535 0.9522)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.9535 0.9522)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.9531 0.9518)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.9473 0.946)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.9446 0.9433)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.9447 0.9434)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.9502 0.9489)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.9536 0.9523)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.9464 0.9451)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.9434 0.9421)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.9511 0.9492)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.9507 0.9488)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.9513 0.9494)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.9497 0.9478)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.9522 0.9503)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.9512 0.9493)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.9494 0.9475)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.9518 0.9499)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.9517 0.9498)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.9491 0.9472)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.952 0.9501)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.9514 0.9495)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.9498 0.9479)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.9502 0.9483)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.9499 0.948)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.9511 0.9492)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.9511 0.9492)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.9555 0.9533)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.9531 0.9509)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.9525 0.9503)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.9523 0.9501)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.952 0.9498)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.9578 0.9556)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.9514 0.9492)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.9529 0.9507)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.9575 0.9553)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.9589 0.9567)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.9614 0.9592)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.9601 0.9579)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.9531 0.9509)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.9618 0.9596)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.9522 0.95)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.9536 0.9514)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.9621 0.9599)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.9606 0.9585)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.9598 0.9577)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.9592 0.9571)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.9605 0.9584)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.9697 0.9676)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.9702 0.9681)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.9642 0.9621)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.9638 0.9617)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.9598 0.9577)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.9702 0.9681)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.9676 0.9655)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.9643 0.9622)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.9672 0.9651)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.9658 0.9637)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.9694 0.9673)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.9598 0.9577)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.9612 0.9591)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.9566 0.9554)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.9601 0.9589)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.96 0.9588)
cellName = DFFPOSX1
int_node_reg/CLK (0.9583 0.9571)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.9559 0.9547)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.9592 0.958)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.9582 0.957)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.9579 0.9567)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.9555 0.9543)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.9582 0.957)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.9557 0.9545)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.9564 0.9552)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.9546 0.9534)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.9578 0.9565)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.9573 0.9561)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.9621 0.9605)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.9674 0.9658)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.9636 0.962)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.9618 0.9602)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.9646 0.963)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.9709 0.9693)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.9714 0.9698)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.9695 0.9679)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.9706 0.969)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.9664 0.9648)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.9668 0.9652)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.9654 0.9638)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.9658 0.9642)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.966 0.9644)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.9645 0.9629)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.9642 0.9626)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.9655 0.9631)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.9649 0.9625)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.9648 0.9624)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.9641 0.9617)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.9649 0.9625)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.9634 0.961)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.9628 0.9604)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.9637 0.9612)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.964 0.9616)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.9644 0.962)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.9661 0.9637)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.9641 0.9617)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.9651 0.9627)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.965 0.9626)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.9654 0.963)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.9652 0.9628)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.9663 0.9639)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.9708 0.9685)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.9715 0.9693)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.9715 0.9693)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.9658 0.9636)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.9666 0.9644)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.9693 0.9671)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.9691 0.9669)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.9676 0.9654)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.9655 0.9633)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.9625 0.9603)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.9669 0.9647)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.9683 0.9661)
cellName = DFFPOSX1
writew_node_reg/CLK (0.9677 0.9655)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.967 0.9648)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.972 0.9698)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.9688 0.9666)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.9863 0.9841)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.9864 0.9842)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.9798 0.9776)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.9832 0.981)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.9852 0.983)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.9854 0.9832)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.9755 0.9733)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.9757 0.9735)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.9757 0.9735)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.9769 0.9747)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.9754 0.9732)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.9758 0.9736)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.9856 0.9834)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.986 0.9838)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.9849 0.9827)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.9787 0.9765)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.9868 0.9846)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.987 0.9841)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.9906 0.9877)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.9869 0.984)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.988 0.9851)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.9882 0.9853)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.9895 0.9866)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.9903 0.9874)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.9836 0.9807)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.985 0.9821)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.9855 0.9826)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.9863 0.9834)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.9871 0.9842)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.9795 0.9766)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.982 0.9791)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.9873 0.9844)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.983 0.9801)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.9854 0.9825)