Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
28.9(ps) ~ 30.025(ps)
1
30.025(ps) ~ 31.15(ps)
0
31.15(ps) ~ 32.275(ps)
1
32.275(ps) ~ 33.4(ps)
2
(max, min, avg, skew) = (33.4(ps) 28.9(ps) 31.825(ps) 4.5(ps))

Output Delay RangeNumber of Buffer
259(ps) ~ 261.8(ps)
2
261.8(ps) ~ 264.6(ps)
0
264.6(ps) ~ 267.4(ps)
1
267.4(ps) ~ 270.2(ps)
1
(max, min, avg, skew) = (270.2(ps) 259(ps) 264.425(ps) 11.2(ps))




Level 2
Input Delay Range Number of Buffer
265.8(ps) ~ 267.88(ps)
3
267.88(ps) ~ 269.96(ps)
2
269.96(ps) ~ 272.04(ps)
1
272.04(ps) ~ 274.12(ps)
1
274.12(ps) ~ 276.2(ps)
3
276.2(ps) ~ 278.28(ps)
3
278.28(ps) ~ 280.36(ps)
3
280.36(ps) ~ 282.44(ps)
1
282.44(ps) ~ 284.52(ps)
0
284.52(ps) ~ 286.6(ps)
3
(max, min, avg, skew) = (286.6(ps) 265.8(ps) 275.89(ps) 20.8(ps))

Output Delay RangeNumber of Buffer
565(ps) ~ 567.6(ps)
4
567.6(ps) ~ 570.2(ps)
3
570.2(ps) ~ 572.8(ps)
0
572.8(ps) ~ 575.4(ps)
3
575.4(ps) ~ 578(ps)
2
578(ps) ~ 580.6(ps)
0
580.6(ps) ~ 583.2(ps)
1
583.2(ps) ~ 585.8(ps)
4
585.8(ps) ~ 588.4(ps)
1
588.4(ps) ~ 591(ps)
2
(max, min, avg, skew) = (591(ps) 565(ps) 576.755(ps) 26(ps))




Level 3
Input Delay Range Number of Buffer
565.6(ps) ~ 570.52(ps)
7
570.52(ps) ~ 575.44(ps)
42
575.44(ps) ~ 580.36(ps)
38
580.36(ps) ~ 585.28(ps)
39
585.28(ps) ~ 590.2(ps)
46
590.2(ps) ~ 595.12(ps)
38
595.12(ps) ~ 600.04(ps)
48
600.04(ps) ~ 604.96(ps)
18
604.96(ps) ~ 609.88(ps)
13
609.88(ps) ~ 614.8(ps)
7
(max, min, avg, skew) = (614.8(ps) 565.6(ps) 587.883(ps) 49.2(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = INVX8
clk_i__L1_I3/A (0.0332 0.0332)
clk_i__L1_I3/Y (0.2614 0.2793)

cellName = INVX8
clk_i__L1_I2/A (0.0289 0.0289)
clk_i__L1_I2/Y (0.259 0.2772)

cellName = INVX8
clk_i__L1_I1/A (0.0334 0.0334)
clk_i__L1_I1/Y (0.2702 0.2893)

cellName = INVX8
clk_i__L1_I0/A (0.0318 0.0318)
clk_i__L1_I0/Y (0.2671 0.286)

LEVEL 2:
cellName = INVX8
clk_i__L2_I19/A (0.2658 0.2837)
clk_i__L2_I19/Y (0.5656 0.5518)

cellName = INVX8
clk_i__L2_I18/A (0.2686 0.2865)
clk_i__L2_I18/Y (0.5675 0.5536)

cellName = INVX8
clk_i__L2_I17/A (0.2684 0.2863)
clk_i__L2_I17/Y (0.569 0.5553)

cellName = INVX8
clk_i__L2_I16/A (0.2767 0.2946)
clk_i__L2_I16/Y (0.5752 0.5612)

cellName = INVX8
clk_i__L2_I15/A (0.2756 0.2935)
clk_i__L2_I15/Y (0.577 0.5635)

cellName = INVX8
clk_i__L2_I14/A (0.2743 0.2925)
clk_i__L2_I14/Y (0.5659 0.5502)

cellName = INVX8
clk_i__L2_I13/A (0.2672 0.2854)
clk_i__L2_I13/Y (0.5688 0.5545)

cellName = INVX8
clk_i__L2_I12/A (0.2767 0.2949)
clk_i__L2_I12/Y (0.565 0.5489)

cellName = INVX8
clk_i__L2_I11/A (0.2677 0.2859)
clk_i__L2_I11/Y (0.5693 0.555)

cellName = INVX8
clk_i__L2_I10/A (0.2711 0.2893)
clk_i__L2_I10/Y (0.5734 0.5592)

cellName = INVX8
clk_i__L2_I9/A (0.2852 0.3043)
clk_i__L2_I9/Y (0.5779 0.5598)

cellName = INVX8
clk_i__L2_I8/A (0.28 0.2991)
clk_i__L2_I8/Y (0.5733 0.5554)

cellName = INVX8
clk_i__L2_I7/A (0.2786 0.2977)
clk_i__L2_I7/Y (0.5843 0.5681)

cellName = INVX8
clk_i__L2_I6/A (0.2741 0.2932)
clk_i__L2_I6/Y (0.5834 0.5678)

cellName = INVX8
clk_i__L2_I5/A (0.2866 0.3057)
clk_i__L2_I5/Y (0.591 0.5747)

cellName = INVX8
clk_i__L2_I4/A (0.2797 0.2986)
clk_i__L2_I4/Y (0.5817 0.5656)

cellName = INVX8
clk_i__L2_I3/A (0.2753 0.2942)
clk_i__L2_I3/Y (0.5845 0.5694)

cellName = INVX8
clk_i__L2_I2/A (0.286 0.3049)
clk_i__L2_I2/Y (0.5908 0.5751)

cellName = INVX8
clk_i__L2_I1/A (0.2824 0.3013)
clk_i__L2_I1/Y (0.5853 0.5693)

cellName = INVX8
clk_i__L2_I0/A (0.2778 0.2967)
clk_i__L2_I0/Y (0.5862 0.571)

LEVEL 3:
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.5725 0.5587)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.572 0.5582)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.5705 0.5567)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.5731 0.5593)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.5742 0.5604)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.5708 0.557)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.5705 0.5567)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.5707 0.5569)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.5726 0.5588)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.5721 0.5583)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.5719 0.5581)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.5713 0.5575)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.5741 0.5603)
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.5675 0.5537)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.5725 0.5587)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.5756 0.5617)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.5795 0.5656)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.5805 0.5666)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.575 0.5611)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.5801 0.5662)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.5797 0.5658)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.5805 0.5666)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.5789 0.565)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.5746 0.5607)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.5755 0.5616)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.5818 0.5679)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.5814 0.5675)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.5822 0.5683)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.5737 0.5598)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.5727 0.5588)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.5802 0.5665)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.5824 0.5687)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.573 0.5593)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.5733 0.5596)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.5729 0.5592)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.5812 0.5675)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.5819 0.5682)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.5815 0.5678)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.5823 0.5686)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.5722 0.5585)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.5785 0.5648)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.5827 0.569)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.5805 0.5668)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.5787 0.565)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.5712 0.5575)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.5838 0.5698)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.5912 0.5772)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.5904 0.5764)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.5829 0.5689)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.5882 0.5742)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.5874 0.5734)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.5913 0.5773)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.5849 0.5709)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.5843 0.5703)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.5831 0.5691)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.5839 0.5699)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.5845 0.5705)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.581 0.567)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.5849 0.5709)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.5836 0.5696)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.5933 0.5798)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.59 0.5765)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.5835 0.57)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.5905 0.577)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.5839 0.5704)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.5913 0.5778)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.5882 0.5747)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.5932 0.5797)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.5916 0.5781)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.5842 0.5707)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.5914 0.5779)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.5882 0.5747)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.5921 0.5786)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.5898 0.5763)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.5862 0.5727)
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.5703 0.5546)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.5747 0.559)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.5713 0.5556)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.5708 0.5551)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.5703 0.5546)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.5775 0.5618)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.5739 0.5582)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.5768 0.5611)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.578 0.5623)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.5729 0.5572)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.5738 0.5581)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.5742 0.5585)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.5743 0.5586)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.5746 0.5589)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.5805 0.5662)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.5791 0.5648)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.5767 0.5624)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.5802 0.5659)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.5804 0.5661)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.5793 0.565)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.5799 0.5656)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.5746 0.5603)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.5764 0.5621)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.5744 0.5601)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.5781 0.5638)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.5793 0.565)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.5795 0.5652)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.5788 0.5645)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.5789 0.5646)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.5744 0.5583)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.5722 0.5561)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.5764 0.5603)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.5769 0.5608)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.5776 0.5615)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.5754 0.5593)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.5739 0.5578)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.5768 0.5607)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.5745 0.5584)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.5777 0.5616)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.5705 0.5544)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.5656 0.5495)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.5717 0.5556)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.5756 0.5595)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.5851 0.5708)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.5755 0.5612)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.584 0.5697)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.5816 0.5673)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.5834 0.5691)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.5728 0.5585)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.5864 0.5721)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.5853 0.571)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.5828 0.5685)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.572 0.5577)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.574 0.5597)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.5755 0.5612)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.5831 0.5688)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.5864 0.5721)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.5777 0.5634)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.582 0.5678)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.5817 0.5675)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.5959 0.5817)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.5995 0.5853)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.603 0.5888)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.5886 0.5744)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.5845 0.5703)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.5917 0.5775)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.5975 0.5833)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.5976 0.5834)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.5971 0.5829)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.6024 0.5882)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.602 0.5878)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.5964 0.5822)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.601 0.5868)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.6025 0.5844)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.6132 0.5951)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.6148 0.5967)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.6143 0.5962)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.5852 0.5671)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.6103 0.5922)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.6076 0.5895)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.6038 0.5857)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.5896 0.5715)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.5988 0.5807)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.5924 0.5743)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.59 0.5719)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.5968 0.5787)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.6123 0.5942)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.5894 0.5715)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.5839 0.566)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.5783 0.5604)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.5798 0.5619)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.5774 0.5595)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.5907 0.5728)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.5914 0.5735)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.5923 0.5744)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.5926 0.5747)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.5783 0.5604)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.5753 0.5574)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.5786 0.5607)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.5789 0.561)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.5876 0.5697)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.5894 0.5732)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.5898 0.5736)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.5881 0.5719)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.5893 0.5731)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.5884 0.5722)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.5916 0.5754)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.5893 0.5731)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.5935 0.5773)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.5925 0.5763)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.5884 0.5722)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.5921 0.5759)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.5897 0.5735)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.59 0.5738)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.5935 0.5773)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.5885 0.5723)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.5899 0.5743)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.5916 0.576)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.5965 0.5809)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.596 0.5804)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.5985 0.5829)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.596 0.5804)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.5916 0.576)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.5951 0.5795)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.6001 0.5845)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.593 0.5774)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.5929 0.5773)
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.5922 0.5766)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.6016 0.586)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.6017 0.5861)
cellName = DFFPOSX1
writew_node_reg/CLK (0.5988 0.5832)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.5988 0.5825)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.601 0.5847)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.6018 0.5855)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.5949 0.5786)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.5947 0.5784)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.6006 0.5843)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.5947 0.5784)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.5994 0.5831)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.5964 0.5801)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.5967 0.5804)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.5992 0.5829)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.6005 0.5842)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.5933 0.577)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.5982 0.5819)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.6014 0.5851)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.5884 0.5723)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.5881 0.572)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.5867 0.5706)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.5842 0.5681)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.5885 0.5724)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.5874 0.5713)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.587 0.5709)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.5858 0.5697)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.5883 0.5722)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.588 0.5719)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.5872 0.5711)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.5864 0.5703)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.5865 0.5704)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.5853 0.5692)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.5889 0.5728)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.5952 0.5801)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.5967 0.5816)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.5878 0.5727)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.5989 0.5838)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.5992 0.5841)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.5911 0.576)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.5879 0.5728)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.5998 0.5847)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.5998 0.5847)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.5993 0.5842)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.5863 0.5712)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.5955 0.5804)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.587 0.5719)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.5872 0.5721)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.5961 0.581)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.597 0.5813)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.5971 0.5814)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.597 0.5813)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.5974 0.5817)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.5956 0.5799)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.5993 0.5836)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.5951 0.5794)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.5974 0.5817)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.5953 0.5796)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.5935 0.5778)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.5938 0.5781)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.5957 0.58)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.5987 0.583)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.5968 0.5811)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.5978 0.5821)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.5974 0.5814)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.5986 0.5826)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.5982 0.5822)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.5908 0.5748)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.5901 0.5741)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.6039 0.5879)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.6052 0.5892)
cellName = DFFPOSX1
int_node_reg/CLK (0.5962 0.5802)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.5942 0.5782)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.5992 0.5832)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.5954 0.5794)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.6013 0.5853)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.6056 0.5896)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.6061 0.5901)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.5979 0.5819)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.609 0.5938)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.6074 0.5922)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.6056 0.5904)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.6087 0.5935)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.6102 0.595)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.6106 0.5954)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.6077 0.5925)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.6046 0.5894)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.6052 0.59)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.6067 0.5915)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.6041 0.5889)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.6082 0.593)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.5977 0.5825)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.5903 0.5751)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.6094 0.5942)