Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
1.7(ps) ~ 1.7(ps) | 1 |
(max, min, avg, skew) = (1.7(ps) 1.7(ps) 1.7(ps) 0(ps))
Output Delay Range | Number of Buffer |
195.1(ps) ~ 195.1(ps) | 1 |
(max, min, avg, skew) = (195.1(ps) 195.1(ps) 195.1(ps) 0(ps))
Level 2
Input Delay Range |
Number of Buffer |
206.6(ps) ~ 207.525(ps) | 1 |
207.525(ps) ~ 208.45(ps) | 0 |
208.45(ps) ~ 209.375(ps) | 1 |
209.375(ps) ~ 210.3(ps) | 2 |
(max, min, avg, skew) = (210.3(ps) 206.6(ps) 208.975(ps) 3.7(ps))
Output Delay Range | Number of Buffer |
390.1(ps) ~ 392.325(ps) | 1 |
392.325(ps) ~ 394.55(ps) | 1 |
394.55(ps) ~ 396.775(ps) | 1 |
396.775(ps) ~ 399(ps) | 1 |
(max, min, avg, skew) = (399(ps) 390.1(ps) 394.2(ps) 8.9(ps))
Level 3
Input Delay Range |
Number of Buffer |
392(ps) ~ 393.05(ps) | 4 |
393.05(ps) ~ 394.1(ps) | 2 |
394.1(ps) ~ 395.15(ps) | 1 |
395.15(ps) ~ 396.2(ps) | 1 |
396.2(ps) ~ 397.25(ps) | 2 |
397.25(ps) ~ 398.3(ps) | 1 |
398.3(ps) ~ 399.35(ps) | 4 |
399.35(ps) ~ 400.4(ps) | 1 |
400.4(ps) ~ 401.45(ps) | 7 |
401.45(ps) ~ 402.5(ps) | 5 |
(max, min, avg, skew) = (402.5(ps) 392(ps) 398.246(ps) 10.5(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = INVX8
clk__L1_I0/A (0.0017 0.0017)
clk__L1_I0/Y (0.1951 0.2084)
LEVEL 2:
cellName = INVX8
clk__L2_I3/A (0.2101 0.2234)
clk__L2_I3/Y (0.3901 0.3719)
cellName = INVX8
clk__L2_I2/A (0.2089 0.2222)
clk__L2_I2/Y (0.3926 0.375)
cellName = INVX8
clk__L2_I1/A (0.2066 0.2199)
clk__L2_I1/Y (0.3951 0.3781)
cellName = INVX8
clk__L2_I0/A (0.2103 0.2236)
clk__L2_I0/Y (0.399 0.382)
LEVEL 3:
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.392 0.3738)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.3928 0.3746)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.3924 0.3742)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.393 0.3748)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.3934 0.3752)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.394 0.3758)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.3944 0.3762)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.396 0.3784)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.3965 0.3789)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.3963 0.3787)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.3987 0.3811)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.4007 0.3831)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.4009 0.3833)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.4012 0.3836)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.3976 0.3806)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.3983 0.3813)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.3992 0.3822)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.3985 0.3815)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.4 0.383)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.4012 0.3842)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.4013 0.3843)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.4013 0.3843)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.4016 0.3846)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.401 0.384)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.4019 0.3849)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.402 0.385)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.4022 0.3852)
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.4025 0.3855)