Clock Tree clk Detail Report
*** NO Transition Time Violation
*** NO Capcitance Violation
Skew Distribution
Level 1
Input Delay Range |
Number of Buffer |
11.7(ps) ~ 13.74(ps) | 2 |
13.74(ps) ~ 15.78(ps) | 7 |
15.78(ps) ~ 17.82(ps) | 0 |
17.82(ps) ~ 19.86(ps) | 0 |
19.86(ps) ~ 21.9(ps) | 0 |
21.9(ps) ~ 23.94(ps) | 1 |
23.94(ps) ~ 25.98(ps) | 8 |
25.98(ps) ~ 28.02(ps) | 5 |
28.02(ps) ~ 30.06(ps) | 0 |
30.06(ps) ~ 32.1(ps) | 5 |
(max, min, avg, skew) = (32.1(ps) 11.7(ps) 22.9429(ps) 20.4(ps))
Detail Phase Delay Report
TOP LEVEL:
clk (0 0)
LEVEL 1:
cellName = DFFPOSX1
block_acc/q_reg_6/CLK (0.0251 0.0251)
cellName = DFFPOSX1
block_acc/q_reg_5/CLK (0.0252 0.0252)
cellName = DFFPOSX1
block_acc/q_reg_4/CLK (0.0313 0.0313)
cellName = DFFPOSX1
block_acc/q_reg_3/CLK (0.0152 0.0152)
cellName = DFFPOSX1
block_acc/q_reg_2/CLK (0.014 0.014)
cellName = DFFPOSX1
block_acc/q_reg_1/CLK (0.0146 0.0146)
cellName = DFFPOSX1
block_acc/q_reg_7/CLK (0.0146 0.0146)
cellName = DFFPOSX1
block_acc/q_reg_0/CLK (0.0129 0.0129)
cellName = DFFPOSX1
block_control/CURRENT_reg_0/CLK (0.0147 0.0147)
cellName = DFFPOSX1
block_control/CURRENT_reg_1/CLK (0.0117 0.0117)
cellName = DFFPOSX1
block_control/CURRENT_reg_2/CLK (0.0141 0.0141)
cellName = DFFPOSX1
block_control/CURRENT_reg_3/CLK (0.014 0.014)
cellName = DFFPOSX1
block_divider/regiA/q_reg_6/CLK (0.0269 0.0269)
cellName = DFFPOSX1
block_divider/regiA/q_reg_5/CLK (0.0271 0.0271)
cellName = DFFPOSX1
block_divider/regiA/q_reg_4/CLK (0.0321 0.0321)
cellName = DFFPOSX1
block_divider/regiA/q_reg_3/CLK (0.0302 0.0302)
cellName = DFFPOSX1
block_divider/regiA/q_reg_2/CLK (0.032 0.032)
cellName = DFFPOSX1
block_divider/regiA/q_reg_1/CLK (0.0253 0.0253)
cellName = DFFPOSX1
block_divider/regiA/q_reg_7/CLK (0.0321 0.0321)
cellName = DFFPOSX1
block_divider/regiA/q_reg_0/CLK (0.024 0.024)
cellName = DFFPOSX1
block_divider/regiB/q_reg_7/CLK (0.0277 0.0277)
cellName = DFFPOSX1
block_divider/regiB/q_reg_6/CLK (0.0262 0.0262)
cellName = DFFPOSX1
block_divider/regiB/q_reg_5/CLK (0.0246 0.0246)
cellName = DFFPOSX1
block_divider/regiB/q_reg_4/CLK (0.0272 0.0272)
cellName = DFFPOSX1
block_divider/regiB/q_reg_3/CLK (0.0254 0.0254)
cellName = DFFPOSX1
block_divider/regiB/q_reg_2/CLK (0.0232 0.0232)
cellName = DFFPOSX1
block_divider/regiB/q_reg_1/CLK (0.0252 0.0252)
cellName = DFFPOSX1
block_divider/regiB/q_reg_0/CLK (0.0258 0.0258)