Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
10.1(ps) ~ 10.3(ps)
1
10.3(ps) ~ 10.5(ps)
1
(max, min, avg, skew) = (10.5(ps) 10.1(ps) 10.3(ps) 0.4(ps))

Output Delay RangeNumber of Buffer
172.7(ps) ~ 175.45(ps)
1
175.45(ps) ~ 178.2(ps)
1
(max, min, avg, skew) = (178.2(ps) 172.7(ps) 175.45(ps) 5.5(ps))




Level 2
Input Delay Range Number of Buffer
183.6(ps) ~ 185.42(ps)
2
185.42(ps) ~ 187.24(ps)
1
187.24(ps) ~ 189.06(ps)
1
189.06(ps) ~ 190.88(ps)
0
190.88(ps) ~ 192.7(ps)
0
192.7(ps) ~ 194.52(ps)
1
194.52(ps) ~ 196.34(ps)
2
196.34(ps) ~ 198.16(ps)
2
198.16(ps) ~ 199.98(ps)
1
199.98(ps) ~ 201.8(ps)
2
(max, min, avg, skew) = (201.8(ps) 183.6(ps) 193.633(ps) 18.2(ps))

Output Delay RangeNumber of Buffer
382.7(ps) ~ 385.02(ps)
1
385.02(ps) ~ 387.34(ps)
0
387.34(ps) ~ 389.66(ps)
2
389.66(ps) ~ 391.98(ps)
0
391.98(ps) ~ 394.3(ps)
1
394.3(ps) ~ 396.62(ps)
1
396.62(ps) ~ 398.94(ps)
1
398.94(ps) ~ 401.26(ps)
3
401.26(ps) ~ 403.58(ps)
1
403.58(ps) ~ 405.9(ps)
2
(max, min, avg, skew) = (405.9(ps) 382.7(ps) 396.467(ps) 23.2(ps))




Level 3
Input Delay Range Number of Buffer
385(ps) ~ 389.41(ps)
8
389.41(ps) ~ 393.82(ps)
20
393.82(ps) ~ 398.23(ps)
18
398.23(ps) ~ 402.64(ps)
48
402.64(ps) ~ 407.05(ps)
60
407.05(ps) ~ 411.46(ps)
48
411.46(ps) ~ 415.87(ps)
42
415.87(ps) ~ 420.28(ps)
27
420.28(ps) ~ 424.69(ps)
12
424.69(ps) ~ 429.1(ps)
13
(max, min, avg, skew) = (429.1(ps) 385(ps) 407.065(ps) 44.1(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = INVX8
clk_i__L1_I1/A (0.0101 0.0101)
clk_i__L1_I1/Y (0.1727 0.1565)

cellName = INVX8
clk_i__L1_I0/A (0.0105 0.0105)
clk_i__L1_I0/Y (0.1782 0.1618)

LEVEL 2:
cellName = INVX8
clk_i__L2_I11/A (0.1839 0.1676)
clk_i__L2_I11/Y (0.3827 0.3855)

cellName = INVX8
clk_i__L2_I10/A (0.196 0.1797)
clk_i__L2_I10/Y (0.3979 0.4002)

cellName = INVX8
clk_i__L2_I9/A (0.1959 0.1796)
clk_i__L2_I9/Y (0.3993 0.4015)

cellName = INVX8
clk_i__L2_I8/A (0.2018 0.1856)
clk_i__L2_I8/Y (0.4059 0.408)

cellName = INVX8
clk_i__L2_I7/A (0.2013 0.1851)
clk_i__L2_I7/Y (0.4048 0.4069)

cellName = INVX8
clk_i__L2_I6/A (0.1979 0.1817)
clk_i__L2_I6/Y (0.4003 0.4026)

cellName = INVX8
clk_i__L2_I5/A (0.1865 0.1701)
clk_i__L2_I5/Y (0.3875 0.3905)

cellName = INVX8
clk_i__L2_I4/A (0.1927 0.1763)
clk_i__L2_I4/Y (0.3923 0.3953)

cellName = INVX8
clk_i__L2_I3/A (0.1836 0.1672)
clk_i__L2_I3/Y (0.3896 0.3922)

cellName = INVX8
clk_i__L2_I2/A (0.1887 0.1724)
clk_i__L2_I2/Y (0.3949 0.3973)

cellName = INVX8
clk_i__L2_I1/A (0.1985 0.1821)
clk_i__L2_I1/Y (0.3999 0.4028)

cellName = INVX8
clk_i__L2_I0/A (0.1968 0.1804)
clk_i__L2_I0/Y (0.4025 0.405)

LEVEL 3:
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.3906 0.3934)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.3947 0.3975)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.3968 0.3995)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.3938 0.3966)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.3875 0.3903)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.3855 0.3883)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.3973 0.4001)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.385 0.3878)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.3851 0.3879)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.392 0.3948)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.3929 0.3956)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.3932 0.396)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.392 0.3948)
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.3932 0.396)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.3956 0.3984)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.3937 0.3965)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.3974 0.4002)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.387 0.3898)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.3888 0.3916)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.3895 0.3923)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.3892 0.392)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.3899 0.3927)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.3906 0.3934)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.3897 0.3925)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.4027 0.405)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.4022 0.4045)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.4058 0.408)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.4073 0.4096)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.4049 0.4072)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.4056 0.4078)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.3999 0.4022)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.4026 0.4048)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.4005 0.4028)
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.4029 0.4052)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.4017 0.404)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.4091 0.4114)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.3997 0.402)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.408 0.4103)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.4066 0.4089)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.4085 0.4108)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.408 0.4103)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.4016 0.4039)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.4014 0.4037)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.4089 0.4112)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.408 0.4103)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.4036 0.4059)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.4032 0.4055)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.4036 0.4059)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.4026 0.4049)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.4056 0.4078)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.4052 0.4074)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.4045 0.4067)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.4041 0.4063)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.4037 0.4059)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.4049 0.4071)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.4125 0.4147)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.4056 0.4078)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.4039 0.4061)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.4046 0.4068)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.4133 0.4155)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.4029 0.4051)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.4026 0.4048)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.4025 0.4047)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.4146 0.4167)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.414 0.4162)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.4146 0.4167)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.4036 0.4058)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.4036 0.4058)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.4021 0.4043)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.4027 0.4049)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.4053 0.4075)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.4093 0.4115)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.4113 0.4134)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.4073 0.4095)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.4194 0.4215)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.4176 0.4197)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.4139 0.416)
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.4187 0.4208)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.4192 0.4213)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.4185 0.4206)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.4191 0.4212)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.4246 0.4267)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.4168 0.4189)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.4169 0.419)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.4234 0.4255)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.4252 0.4273)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.4243 0.4264)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.425 0.4271)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.4237 0.4258)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.4252 0.4273)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.4253 0.4274)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.4206 0.4227)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.4252 0.4273)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.4136 0.4157)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.4065 0.4086)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.4065 0.4086)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.4161 0.4182)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.4154 0.4175)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.4157 0.4178)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.4086 0.4107)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.4127 0.4147)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.4091 0.4112)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.4091 0.4112)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.4093 0.4114)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.41 0.4121)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.4076 0.4097)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.4141 0.4162)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.4079 0.41)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.4104 0.4125)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.4098 0.4119)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.4183 0.4204)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.4111 0.4132)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.4108 0.4129)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.4208 0.4228)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.4207 0.4228)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.4198 0.4219)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.421 0.4231)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.4173 0.4194)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.4162 0.4183)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.4121 0.4142)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.412 0.4141)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.4122 0.4144)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.4111 0.4132)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.4104 0.4125)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.4084 0.4107)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.4154 0.4177)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.4151 0.4174)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.4144 0.4167)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.4029 0.4051)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.406 0.4083)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.4049 0.4072)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.4038 0.4061)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.411 0.4132)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.4096 0.4119)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.4094 0.4117)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.4126 0.4149)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.4139 0.4161)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.411 0.4133)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.4119 0.4142)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.4172 0.4195)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.414 0.4163)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.4126 0.4149)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.415 0.4173)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.4064 0.4087)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.4083 0.4106)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.4159 0.4182)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.4167 0.419)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.4171 0.4194)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.4134 0.4157)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.4046 0.4076)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.4044 0.4074)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.3945 0.3974)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.3923 0.3953)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.3989 0.4019)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.3907 0.3937)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.3928 0.3958)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.3909 0.3939)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.4038 0.4068)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.3964 0.3994)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.4036 0.4066)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.4004 0.4034)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.3894 0.3924)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.3936 0.3966)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.3961 0.3991)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.3896 0.3926)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.3921 0.3951)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.3958 0.3988)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.3973 0.4003)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.3984 0.4014)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.3981 0.4011)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.3985 0.4015)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.4018 0.4048)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.4035 0.4065)
cellName = DFFPOSX1
writew_node_reg/CLK (0.3986 0.4016)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.4065 0.4094)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.4093 0.4123)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.4012 0.4042)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.4009 0.4039)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.3971 0.4001)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.4088 0.4118)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.4028 0.4058)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.3977 0.4007)
cellName = DFFPOSX1
int_node_reg/CLK (0.4005 0.4035)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.4079 0.4109)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.4052 0.4081)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.3976 0.4006)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.3933 0.3963)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.3955 0.3986)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.4018 0.4048)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.3998 0.4028)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.3944 0.3974)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.4 0.403)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.3988 0.4018)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.3985 0.4015)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.3977 0.4007)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.41 0.413)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.4099 0.4129)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.4023 0.4049)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.4043 0.4068)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.4008 0.4033)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.4014 0.404)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.4008 0.4034)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.4018 0.4043)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.4009 0.4035)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.4012 0.4038)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.3994 0.402)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.4001 0.4027)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.401 0.4036)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.4003 0.4029)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.4021 0.4047)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.4037 0.4063)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.3994 0.402)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.4046 0.4072)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.4051 0.4077)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.405 0.4076)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.3987 0.4013)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.3958 0.3984)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.4002 0.4028)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.4013 0.4039)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.4019 0.4045)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.4044 0.407)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.4029 0.4055)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.4144 0.4168)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.4156 0.418)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.4137 0.4161)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.4204 0.4228)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.403 0.4054)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.4021 0.4045)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.4036 0.406)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.4032 0.4056)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.4011 0.4035)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.4205 0.4229)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.413 0.4155)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.4191 0.4215)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.4155 0.4179)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.412 0.4144)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.4126 0.4151)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.4081 0.4105)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.4165 0.4189)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.4196 0.422)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.4008 0.4033)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.4175 0.4199)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.4181 0.4205)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.3996 0.402)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.4051 0.4075)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.4014 0.4039)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.4153 0.4177)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.4094 0.4123)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.4084 0.4113)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.4088 0.4117)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.4096 0.4125)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.4042 0.4071)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.4113 0.4142)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.4103 0.4132)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.4041 0.407)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.4031 0.406)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.4122 0.4151)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.4088 0.4117)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.4054 0.4083)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.4074 0.4103)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.4102 0.4131)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.4099 0.4128)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.4065 0.4094)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.4063 0.4092)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.4069 0.4098)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.406 0.4089)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.4055 0.4084)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.4046 0.4075)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.4086 0.4115)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.4123 0.4151)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.407 0.4099)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.4247 0.4272)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.4281 0.4306)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.4239 0.4264)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.4247 0.4272)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.4275 0.43)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.4268 0.4293)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.4259 0.4284)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.4193 0.4219)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.416 0.4185)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.4147 0.4172)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.4165 0.419)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.4122 0.4147)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.4104 0.4129)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.4156 0.4182)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.4289 0.4314)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.4291 0.4316)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.4111 0.4136)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.4131 0.4156)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.4172 0.4197)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.4141 0.4166)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.4147 0.4172)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.4139 0.4164)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.4119 0.4144)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.4174 0.4199)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.4244 0.4269)