Clock Tree clk_i Detail Report


*** NO Transition Time Violation
*** NO Capcitance Violation

Skew Distribution

Level 1
Input Delay Range Number of Buffer
2.7(ps) ~ 2.7(ps)
1
(max, min, avg, skew) = (2.7(ps) 2.7(ps) 2.7(ps) 0(ps))

Output Delay RangeNumber of Buffer
373.7(ps) ~ 373.7(ps)
1
(max, min, avg, skew) = (373.7(ps) 373.7(ps) 373.7(ps) 0(ps))




Level 2
Input Delay Range Number of Buffer
376.8(ps) ~ 377.633(ps)
1
377.633(ps) ~ 378.467(ps)
1
378.467(ps) ~ 379.3(ps)
1
(max, min, avg, skew) = (379.3(ps) 376.8(ps) 378.033(ps) 2.5(ps))

Output Delay RangeNumber of Buffer
648.9(ps) ~ 651.567(ps)
2
651.567(ps) ~ 654.233(ps)
0
654.233(ps) ~ 656.9(ps)
1
(max, min, avg, skew) = (656.9(ps) 648.9(ps) 651.867(ps) 8(ps))




Level 3
Input Delay Range Number of Buffer
651.7(ps) ~ 654.02(ps)
1
654.02(ps) ~ 656.34(ps)
4
656.34(ps) ~ 658.66(ps)
5
658.66(ps) ~ 660.98(ps)
2
660.98(ps) ~ 663.3(ps)
1
663.3(ps) ~ 665.62(ps)
0
665.62(ps) ~ 667.94(ps)
2
667.94(ps) ~ 670.26(ps)
1
670.26(ps) ~ 672.58(ps)
1
672.58(ps) ~ 674.9(ps)
1
(max, min, avg, skew) = (674.9(ps) 651.7(ps) 660.672(ps) 23.2(ps))

Output Delay RangeNumber of Buffer
901.3(ps) ~ 905.27(ps)
3
905.27(ps) ~ 909.24(ps)
3
909.24(ps) ~ 913.21(ps)
0
913.21(ps) ~ 917.18(ps)
4
917.18(ps) ~ 921.15(ps)
3
921.15(ps) ~ 925.12(ps)
2
925.12(ps) ~ 929.09(ps)
1
929.09(ps) ~ 933.06(ps)
0
933.06(ps) ~ 937.03(ps)
1
937.03(ps) ~ 941(ps)
1
(max, min, avg, skew) = (941(ps) 901.3(ps) 916.533(ps) 39.7(ps))




Level 4
Input Delay Range Number of Buffer
905.1(ps) ~ 910.59(ps)
23
910.59(ps) ~ 916.08(ps)
31
916.08(ps) ~ 921.57(ps)
63
921.57(ps) ~ 927.06(ps)
76
927.06(ps) ~ 932.55(ps)
39
932.55(ps) ~ 938.04(ps)
28
938.04(ps) ~ 943.53(ps)
7
943.53(ps) ~ 949.02(ps)
5
949.02(ps) ~ 954.51(ps)
17
954.51(ps) ~ 960(ps)
7
(max, min, avg, skew) = (960(ps) 905.1(ps) 925.821(ps) 54.9(ps))






Detail Phase Delay Report

TOP LEVEL:
clk_i (0 0)

LEVEL 1:
cellName = CLKBUF1
clk_i__L1_I0/A (0.0027 0.0027)
clk_i__L1_I0/Y (0.3737 0.3727)

LEVEL 2:
cellName = INVX8
clk_i__L2_I2/A (0.3768 0.3758)
clk_i__L2_I2/Y (0.6498 0.6342)

cellName = INVX8
clk_i__L2_I1/A (0.3793 0.3783)
clk_i__L2_I1/Y (0.6489 0.6337)

cellName = INVX8
clk_i__L2_I0/A (0.378 0.377)
clk_i__L2_I0/Y (0.6569 0.6408)

LEVEL 3:
cellName = INVX8
clk_i__L3_I17/A (0.6599 0.6443)
clk_i__L3_I17/Y (0.9074 0.9033)

cellName = INVX8
clk_i__L3_I16/A (0.656 0.6404)
clk_i__L3_I16/Y (0.908 0.9035)

cellName = INVX8
clk_i__L3_I15/A (0.6567 0.6411)
clk_i__L3_I15/Y (0.9089 0.9044)

cellName = INVX8
clk_i__L3_I14/A (0.6585 0.6429)
clk_i__L3_I14/Y (0.9179 0.9128)

cellName = INVX8
clk_i__L3_I13/A (0.6559 0.6403)
clk_i__L3_I13/Y (0.9172 0.9119)

cellName = INVX8
clk_i__L3_I12/A (0.6616 0.646)
clk_i__L3_I12/Y (0.921 0.9159)

cellName = INVX8
clk_i__L3_I11/A (0.6552 0.64)
clk_i__L3_I11/Y (0.9034 0.8987)

cellName = INVX8
clk_i__L3_I10/A (0.6517 0.6365)
clk_i__L3_I10/Y (0.9013 0.8965)

cellName = INVX8
clk_i__L3_I9/A (0.6553 0.6401)
clk_i__L3_I9/Y (0.9042 0.8995)

cellName = INVX8
clk_i__L3_I8/A (0.6571 0.6419)
clk_i__L3_I8/Y (0.9138 0.9085)

cellName = INVX8
clk_i__L3_I7/A (0.6579 0.6427)
clk_i__L3_I7/Y (0.9167 0.9112)

cellName = INVX8
clk_i__L3_I6/A (0.6567 0.6415)
clk_i__L3_I6/Y (0.9134 0.9081)

cellName = INVX8
clk_i__L3_I5/A (0.6669 0.6508)
clk_i__L3_I5/Y (0.9165 0.9128)

cellName = INVX8
clk_i__L3_I4/A (0.6693 0.6532)
clk_i__L3_I4/Y (0.9225 0.9185)

cellName = INVX8
clk_i__L3_I3/A (0.659 0.6429)
clk_i__L3_I3/Y (0.9221 0.9173)

cellName = INVX8
clk_i__L3_I2/A (0.6675 0.6514)
clk_i__L3_I2/Y (0.9278 0.9232)

cellName = INVX8
clk_i__L3_I1/A (0.6749 0.6588)
clk_i__L3_I1/Y (0.9345 0.9299)

cellName = INVX8
clk_i__L3_I0/A (0.672 0.6559)
clk_i__L3_I0/Y (0.941 0.9358)

LEVEL 4:
cellName = DFFPOSX1
stack_reg_reg_5_7/CLK (0.9181 0.914)
cellName = DFFPOSX1
stack_reg_reg_0_7/CLK (0.9132 0.9091)
cellName = DFFPOSX1
stack_reg_reg_2_7/CLK (0.9136 0.9095)
cellName = DFFPOSX1
stack_reg_reg_3_7/CLK (0.9114 0.9073)
cellName = DFFPOSX1
stack_reg_reg_7_9/CLK (0.9171 0.913)
cellName = DFFPOSX1
stack_reg_reg_7_7/CLK (0.917 0.9129)
cellName = DFFPOSX1
stack_reg_reg_7_5/CLK (0.9158 0.9117)
cellName = DFFPOSX1
stack_reg_reg_6_9/CLK (0.918 0.9139)
cellName = DFFPOSX1
stack_reg_reg_5_8/CLK (0.919 0.9149)
cellName = DFFPOSX1
stack_reg_reg_5_5/CLK (0.9188 0.9146)
cellName = DFFPOSX1
stack_reg_reg_4_8/CLK (0.9176 0.9135)
cellName = DFFPOSX1
stack_reg_reg_3_1/CLK (0.9129 0.9088)
cellName = DFFPOSX1
stack_reg_reg_2_8/CLK (0.914 0.9099)
cellName = DFFPOSX1
stack_reg_reg_1_8/CLK (0.9098 0.9057)
cellName = DFFPOSX1
stack_reg_reg_1_7/CLK (0.912 0.9079)
cellName = DFFPOSX1
stack_reg_reg_0_8/CLK (0.912 0.9079)
cellName = DFFPOSX1
trisb_reg_reg_2/CLK (0.9147 0.9102)
cellName = DFFPOSX1
fsr_reg_reg_0/CLK (0.9107 0.9062)
cellName = DFFPOSX1
inst_reg_reg_0/CLK (0.9176 0.9131)
cellName = DFFPOSX1
inst_reg_reg_1/CLK (0.9108 0.9063)
cellName = DFFPOSX1
inst_reg_reg_2/CLK (0.9197 0.9152)
cellName = DFFPOSX1
inst_reg_reg_3/CLK (0.9194 0.9149)
cellName = DFFPOSX1
inst_reg_reg_5/CLK (0.9169 0.9124)
cellName = DFFPOSX1
inst_reg_reg_6/CLK (0.9187 0.9142)
cellName = DFFPOSX1
status_reg_reg_5/CLK (0.9133 0.9088)
cellName = DFFPOSX1
status_reg_reg_7/CLK (0.9099 0.9054)
cellName = DFFPOSX1
intcon_reg_reg_5/CLK (0.9201 0.9156)
cellName = DFFPOSX1
ram_i_node_reg_5/CLK (0.9152 0.9107)
cellName = DFFPOSX1
fsr_reg_reg_2/CLK (0.9105 0.906)
cellName = DFFPOSX1
pclath_reg_reg_4/CLK (0.9135 0.909)
cellName = DFFPOSX1
pclath_reg_reg_3/CLK (0.9125 0.908)
cellName = DFFPOSX1
option_reg_reg_4/CLK (0.9142 0.9097)
cellName = DFFPOSX1
inc_pc_node_reg_6/CLK (0.9298 0.9253)
cellName = DFFPOSX1
inc_pc_node_reg_5/CLK (0.917 0.9125)
cellName = DFFPOSX1
stack_reg_reg_0_9/CLK (0.9256 0.9211)
cellName = DFFPOSX1
stack_reg_reg_1_5/CLK (0.9267 0.9222)
cellName = DFFPOSX1
stack_reg_reg_1_9/CLK (0.9247 0.9202)
cellName = DFFPOSX1
stack_reg_reg_2_9/CLK (0.9242 0.9197)
cellName = DFFPOSX1
stack_reg_reg_3_9/CLK (0.9238 0.9193)
cellName = DFFPOSX1
pc_reg_reg_4/CLK (0.9277 0.9232)
cellName = DFFPOSX1
pc_reg_reg_5/CLK (0.9225 0.918)
cellName = DFFPOSX1
pc_reg_reg_6/CLK (0.929 0.9245)
cellName = DFFPOSX1
pc_reg_reg_8/CLK (0.9259 0.9214)
cellName = DFFPOSX1
inc_pc_node_reg_7/CLK (0.9144 0.9099)
cellName = DFFPOSX1
inc_pc_node_reg_8/CLK (0.9263 0.9218)
cellName = DFFPOSX1
pc_reg_reg_7/CLK (0.9154 0.9109)
cellName = DFFPOSX1
inc_pc_node_reg_4/CLK (0.9297 0.9252)
cellName = DFFPOSX1
intcon_reg_reg_6/CLK (0.9158 0.9113)
cellName = DFFPOSX1
option_reg_reg_2/CLK (0.921 0.9159)
cellName = DFFPOSX1
option_reg_reg_3/CLK (0.9203 0.9152)
cellName = DFFPOSX1
option_reg_reg_5/CLK (0.922 0.9169)
cellName = DFFPOSX1
trisa_reg_reg_0/CLK (0.922 0.9169)
cellName = DFFPOSX1
trisa_reg_reg_4/CLK (0.9234 0.9183)
cellName = DFFPOSX1
trisb_reg_reg_0/CLK (0.923 0.9179)
cellName = DFFPOSX1
trisb_reg_reg_1/CLK (0.9251 0.92)
cellName = DFFPOSX1
trisb_reg_reg_3/CLK (0.9262 0.9211)
cellName = DFFPOSX1
trisb_reg_reg_4/CLK (0.9198 0.9147)
cellName = DFFPOSX1
trisb_reg_reg_5/CLK (0.9216 0.9165)
cellName = DFFPOSX1
portb_o_reg_reg_0/CLK (0.9243 0.9192)
cellName = DFFPOSX1
portb_o_reg_reg_1/CLK (0.9246 0.9195)
cellName = DFFPOSX1
portb_o_reg_reg_4/CLK (0.9264 0.9213)
cellName = DFFPOSX1
portb_o_reg_reg_5/CLK (0.9231 0.918)
cellName = DFFPOSX1
portb_i_sync_reg_reg_2/CLK (0.926 0.9209)
cellName = DFFPOSX1
portb_i_sync_reg_reg_3/CLK (0.9243 0.9192)
cellName = DFFPOSX1
porta_o_reg_reg_4/CLK (0.9214 0.9162)
cellName = DFFPOSX1
intcon_reg_reg_0/CLK (0.9214 0.9161)
cellName = DFFPOSX1
status_reg_reg_6/CLK (0.9277 0.9224)
cellName = DFFPOSX1
w_reg_reg_3/CLK (0.9238 0.9185)
cellName = DFFPOSX1
aluinp1_reg_reg_3/CLK (0.9238 0.9185)
cellName = DFFPOSX1
ram_i_node_reg_3/CLK (0.9291 0.9238)
cellName = DFFPOSX1
inst_reg_reg_8/CLK (0.9254 0.9201)
cellName = DFFPOSX1
w_reg_reg_7/CLK (0.9238 0.9185)
cellName = DFFPOSX1
status_reg_reg_3/CLK (0.9296 0.9243)
cellName = DFFPOSX1
pclath_reg_reg_0/CLK (0.9218 0.9165)
cellName = DFFPOSX1
pclath_reg_reg_1/CLK (0.9207 0.9154)
cellName = DFFPOSX1
aluout_reg_reg_6/CLK (0.9215 0.9162)
cellName = DFFPOSX1
ram_i_node_reg_0/CLK (0.9231 0.9178)
cellName = DFFPOSX1
ram_i_node_reg_7/CLK (0.9238 0.9185)
cellName = DFFPOSX1
ram_i_node_reg_6/CLK (0.9281 0.9228)
cellName = DFFPOSX1
w_reg_reg_6/CLK (0.9231 0.9178)
cellName = DFFPOSX1
pclath_reg_reg_2/CLK (0.9208 0.9155)
cellName = DFFPOSX1
w_reg_reg_5/CLK (0.9214 0.9161)
cellName = DFFPOSX1
stack_reg_reg_6_7/CLK (0.9253 0.9202)
cellName = DFFPOSX1
stack_reg_reg_5_1/CLK (0.9253 0.9202)
cellName = DFFPOSX1
stack_reg_reg_2_1/CLK (0.9241 0.919)
cellName = DFFPOSX1
stack_reg_reg_6_5/CLK (0.9253 0.9202)
cellName = DFFPOSX1
stack_reg_reg_4_1/CLK (0.9238 0.9187)
cellName = DFFPOSX1
stack_reg_reg_4_7/CLK (0.9247 0.9196)
cellName = DFFPOSX1
stack_reg_reg_7_1/CLK (0.9247 0.9196)
cellName = DFFPOSX1
stack_reg_reg_6_8/CLK (0.9261 0.921)
cellName = DFFPOSX1
stack_reg_reg_7_8/CLK (0.9256 0.9205)
cellName = DFFPOSX1
stack_reg_reg_7_6/CLK (0.9264 0.9213)
cellName = DFFPOSX1
stack_reg_reg_6_6/CLK (0.9286 0.9235)
cellName = DFFPOSX1
stack_reg_reg_5_6/CLK (0.9284 0.9233)
cellName = DFFPOSX1
stack_reg_reg_4_5/CLK (0.9266 0.9215)
cellName = DFFPOSX1
stack_reg_reg_6_1/CLK (0.9261 0.921)
cellName = DFFPOSX1
pc_reg_reg_2/CLK (0.9269 0.9218)
cellName = DFFPOSX1
stack_reg_reg_1_1/CLK (0.9267 0.9216)
cellName = DFFPOSX1
stack_reg_reg_6_2/CLK (0.9278 0.9227)
cellName = DFFPOSX1
portb_o_reg_reg_6/CLK (0.9109 0.9062)
cellName = DFFPOSX1
inst_reg_reg_9/CLK (0.9051 0.9004)
cellName = DFFPOSX1
option_reg_reg_7/CLK (0.9089 0.9042)
cellName = DFFPOSX1
fsr_reg_reg_1/CLK (0.9112 0.9065)
cellName = DFFPOSX1
fsr_reg_reg_3/CLK (0.9107 0.906)
cellName = DFFPOSX1
fsr_reg_reg_4/CLK (0.9084 0.9037)
cellName = DFFPOSX1
fsr_reg_reg_5/CLK (0.9098 0.9051)
cellName = DFFPOSX1
fsr_reg_reg_6/CLK (0.9053 0.9006)
cellName = DFFPOSX1
porta_o_reg_reg_2/CLK (0.9057 0.901)
cellName = DFFPOSX1
trisb_reg_reg_6/CLK (0.9073 0.9026)
cellName = DFFPOSX1
trisb_reg_reg_7/CLK (0.9093 0.9046)
cellName = DFFPOSX1
portb_o_reg_reg_2/CLK (0.9065 0.9018)
cellName = DFFPOSX1
portb_o_reg_reg_3/CLK (0.9077 0.903)
cellName = DFFPOSX1
ram_adr_reg_reg_7/CLK (0.9105 0.9058)
cellName = DFFPOSX1
fsr_reg_reg_7/CLK (0.9096 0.9049)
cellName = DFFPOSX1
portb_o_reg_reg_7/CLK (0.9106 0.9059)
cellName = DFFPOSX1
inc_pc_node_reg_11/CLK (0.9104 0.9056)
cellName = DFFPOSX1
ram_adr_reg_reg_6/CLK (0.9189 0.9141)
cellName = DFFPOSX1
inst_reg_reg_10/CLK (0.9198 0.915)
cellName = DFFPOSX1
inst_reg_reg_4/CLK (0.911 0.9062)
cellName = DFFPOSX1
inc_pc_node_reg_10/CLK (0.9101 0.9053)
cellName = DFFPOSX1
pc_reg_reg_9/CLK (0.9109 0.9061)
cellName = DFFPOSX1
pc_reg_reg_10/CLK (0.91 0.9052)
cellName = DFFPOSX1
writeram_reg_reg/CLK (0.9083 0.9035)
cellName = DFFPOSX1
ram_adr_reg_reg_0/CLK (0.9179 0.9131)
cellName = DFFPOSX1
ram_adr_reg_reg_1/CLK (0.9167 0.9119)
cellName = DFFPOSX1
ram_adr_reg_reg_2/CLK (0.9152 0.9103)
cellName = DFFPOSX1
ram_adr_reg_reg_3/CLK (0.9121 0.9072)
cellName = DFFPOSX1
ram_adr_reg_reg_4/CLK (0.9133 0.9085)
cellName = DFFPOSX1
ram_adr_reg_reg_8/CLK (0.9169 0.9121)
cellName = DFFPOSX1
ram_adr_reg_reg_5/CLK (0.9118 0.907)
cellName = DFFPOSX1
option_reg_reg_6/CLK (0.9194 0.9146)
cellName = DFFPOSX1
inc_pc_node_reg_12/CLK (0.9075 0.9028)
cellName = DFFPOSX1
stack_reg_reg_7_4/CLK (0.9245 0.9198)
cellName = DFFPOSX1
stack_reg_reg_6_12/CLK (0.9223 0.9176)
cellName = DFFPOSX1
stack_reg_reg_6_10/CLK (0.9241 0.9194)
cellName = DFFPOSX1
stack_reg_reg_6_4/CLK (0.9249 0.9202)
cellName = DFFPOSX1
stack_reg_reg_6_3/CLK (0.919 0.9143)
cellName = DFFPOSX1
stack_reg_reg_3_8/CLK (0.926 0.9213)
cellName = DFFPOSX1
stack_reg_reg_3_5/CLK (0.9267 0.922)
cellName = DFFPOSX1
stack_reg_reg_2_5/CLK (0.9266 0.9219)
cellName = DFFPOSX1
stack_reg_reg_2_4/CLK (0.9147 0.9101)
cellName = DFFPOSX1
stack_reg_reg_1_3/CLK (0.9056 0.9009)
cellName = DFFPOSX1
stack_reg_reg_0_4/CLK (0.9125 0.9078)
cellName = DFFPOSX1
stack_reg_reg_3_4/CLK (0.9172 0.9125)
cellName = DFFPOSX1
stack_reg_reg_0_5/CLK (0.927 0.9223)
cellName = DFFPOSX1
inc_pc_node_reg_9/CLK (0.9071 0.9024)
cellName = DFFPOSX1
stack_reg_reg_1_4/CLK (0.9096 0.9049)
cellName = DFFPOSX1
pc_reg_reg_11/CLK (0.9194 0.9141)
cellName = DFFPOSX1
stack_reg_reg_0_3/CLK (0.919 0.9137)
cellName = DFFPOSX1
stack_reg_reg_1_11/CLK (0.919 0.9137)
cellName = DFFPOSX1
stack_reg_reg_2_12/CLK (0.9202 0.9149)
cellName = DFFPOSX1
stack_reg_reg_3_12/CLK (0.9229 0.9176)
cellName = DFFPOSX1
stack_reg_reg_3_11/CLK (0.9216 0.9163)
cellName = DFFPOSX1
stack_reg_reg_3_10/CLK (0.9191 0.9138)
cellName = DFFPOSX1
stack_reg_reg_3_3/CLK (0.9231 0.9178)
cellName = DFFPOSX1
stack_reg_reg_2_11/CLK (0.9226 0.9173)
cellName = DFFPOSX1
stack_reg_reg_2_10/CLK (0.9176 0.9123)
cellName = DFFPOSX1
stack_reg_reg_2_3/CLK (0.9235 0.9182)
cellName = DFFPOSX1
stack_reg_reg_1_12/CLK (0.9193 0.914)
cellName = DFFPOSX1
stack_reg_reg_1_10/CLK (0.9183 0.913)
cellName = DFFPOSX1
stack_reg_reg_0_12/CLK (0.9178 0.9125)
cellName = DFFPOSX1
stack_reg_reg_0_11/CLK (0.9172 0.9119)
cellName = DFFPOSX1
stack_reg_reg_0_10/CLK (0.9193 0.914)
cellName = DFFPOSX1
pc_reg_reg_12/CLK (0.9198 0.9145)
cellName = DFFPOSX1
stack_reg_reg_4_9/CLK (0.9237 0.9182)
cellName = DFFPOSX1
stack_reg_reg_4_10/CLK (0.921 0.9155)
cellName = DFFPOSX1
stack_reg_reg_4_12/CLK (0.9212 0.9157)
cellName = DFFPOSX1
stack_reg_reg_5_3/CLK (0.9205 0.915)
cellName = DFFPOSX1
stack_reg_reg_5_4/CLK (0.9193 0.9138)
cellName = DFFPOSX1
stack_reg_reg_5_9/CLK (0.9267 0.9212)
cellName = DFFPOSX1
stack_reg_reg_5_10/CLK (0.918 0.9125)
cellName = DFFPOSX1
stack_reg_reg_5_11/CLK (0.9198 0.9143)
cellName = DFFPOSX1
stack_reg_reg_5_12/CLK (0.9256 0.9201)
cellName = DFFPOSX1
stack_reg_reg_6_11/CLK (0.9283 0.9228)
cellName = DFFPOSX1
stack_reg_reg_7_3/CLK (0.9305 0.925)
cellName = DFFPOSX1
stack_reg_reg_7_11/CLK (0.9292 0.9237)
cellName = DFFPOSX1
stack_reg_reg_4_11/CLK (0.9201 0.9146)
cellName = DFFPOSX1
stack_reg_reg_7_10/CLK (0.9313 0.9257)
cellName = DFFPOSX1
stack_reg_reg_4_4/CLK (0.9196 0.9141)
cellName = DFFPOSX1
stack_reg_reg_4_3/CLK (0.9214 0.9159)
cellName = DFFPOSX1
stack_reg_reg_7_12/CLK (0.9313 0.9258)
cellName = DFFPOSX1
trisa_reg_reg_3/CLK (0.9209 0.9156)
cellName = DFFPOSX1
trisa_reg_reg_1/CLK (0.919 0.9137)
cellName = DFFPOSX1
trisa_reg_reg_2/CLK (0.9179 0.9126)
cellName = DFFPOSX1
porta_o_reg_reg_0/CLK (0.9204 0.9151)
cellName = DFFPOSX1
porta_i_sync_reg_reg_1/CLK (0.9374 0.9321)
cellName = DFFPOSX1
porta_i_sync_reg_reg_2/CLK (0.9377 0.9324)
cellName = DFFPOSX1
porta_i_sync_reg_reg_3/CLK (0.9291 0.9238)
cellName = DFFPOSX1
porta_i_sync_reg_reg_4/CLK (0.9267 0.9215)
cellName = DFFPOSX1
portb_i_sync_reg_reg_0/CLK (0.9192 0.9139)
cellName = DFFPOSX1
portb_i_sync_reg_reg_1/CLK (0.9379 0.9326)
cellName = DFFPOSX1
portb_i_sync_reg_reg_4/CLK (0.9354 0.9301)
cellName = DFFPOSX1
portb_i_sync_reg_reg_5/CLK (0.9308 0.9255)
cellName = DFFPOSX1
portb_i_sync_reg_reg_6/CLK (0.9343 0.929)
cellName = DFFPOSX1
portb_i_sync_reg_reg_7/CLK (0.9331 0.9278)
cellName = DFFPOSX1
porta_i_sync_reg_reg_0/CLK (0.9365 0.9312)
cellName = DFFPOSX1
porta_o_reg_reg_1/CLK (0.9188 0.9135)
cellName = DFFPOSX1
porta_o_reg_reg_3/CLK (0.9226 0.9173)
cellName = DFFPOSX1
stack_reg_reg_7_0/CLK (0.92 0.9163)
cellName = DFFPOSX1
stack_reg_reg_0_0/CLK (0.9266 0.9229)
cellName = DFFPOSX1
stack_reg_reg_1_0/CLK (0.9263 0.9226)
cellName = DFFPOSX1
int_node_reg/CLK (0.9251 0.9214)
cellName = DFFPOSX1
stack_pnt_reg_reg_1/CLK (0.9192 0.9155)
cellName = DFFPOSX1
stack_reg_reg_0_2/CLK (0.9255 0.9218)
cellName = DFFPOSX1
stack_pnt_reg_reg_2/CLK (0.9246 0.9209)
cellName = DFFPOSX1
state_reg_reg_1/CLK (0.9246 0.9209)
cellName = DFFPOSX1
exec_op_reg_reg/CLK (0.9212 0.9175)
cellName = DFFPOSX1
status_reg_reg_4/CLK (0.9246 0.9209)
cellName = DFFPOSX1
stack_pnt_reg_reg_0/CLK (0.9205 0.9168)
cellName = DFFPOSX1
intstart_reg_reg/CLK (0.9233 0.9196)
cellName = DFFPOSX1
sleepflag_reg_reg/CLK (0.918 0.9143)
cellName = DFFPOSX1
intcon_reg_reg_1/CLK (0.9244 0.9207)
cellName = DFFPOSX1
state_reg_reg_0/CLK (0.9243 0.9206)
cellName = DFFPOSX1
stack_reg_reg_2_2/CLK (0.924 0.92)
cellName = DFFPOSX1
stack_reg_reg_1_2/CLK (0.9337 0.9297)
cellName = DFFPOSX1
stack_reg_reg_5_0/CLK (0.9254 0.9214)
cellName = DFFPOSX1
stack_reg_reg_3_6/CLK (0.9273 0.9233)
cellName = DFFPOSX1
stack_reg_reg_4_0/CLK (0.9264 0.9224)
cellName = DFFPOSX1
stack_reg_reg_0_6/CLK (0.936 0.932)
cellName = DFFPOSX1
stack_reg_reg_1_6/CLK (0.9365 0.9324)
cellName = DFFPOSX1
stack_reg_reg_2_0/CLK (0.9348 0.9308)
cellName = DFFPOSX1
stack_reg_reg_2_6/CLK (0.9357 0.9317)
cellName = DFFPOSX1
stack_reg_reg_3_0/CLK (0.9322 0.9282)
cellName = DFFPOSX1
stack_reg_reg_3_2/CLK (0.9324 0.9284)
cellName = DFFPOSX1
stack_reg_reg_4_2/CLK (0.931 0.927)
cellName = DFFPOSX1
stack_reg_reg_4_6/CLK (0.9316 0.9276)
cellName = DFFPOSX1
stack_reg_reg_5_2/CLK (0.9319 0.9279)
cellName = DFFPOSX1
stack_reg_reg_6_0/CLK (0.9267 0.9227)
cellName = DFFPOSX1
stack_reg_reg_7_2/CLK (0.9268 0.9228)
cellName = DFFPOSX1
pc_reg_reg_1/CLK (0.9337 0.9289)
cellName = DFFPOSX1
stack_reg_reg_0_1/CLK (0.9331 0.9283)
cellName = DFFPOSX1
pc_reg_reg_0/CLK (0.9322 0.9273)
cellName = DFFPOSX1
intcon_reg_reg_3/CLK (0.9294 0.9246)
cellName = DFFPOSX1
ram_i_node_reg_1/CLK (0.9303 0.9255)
cellName = DFFPOSX1
inc_pc_node_reg_0/CLK (0.9293 0.9245)
cellName = DFFPOSX1
intcon_reg_reg_4/CLK (0.9272 0.9224)
cellName = DFFPOSX1
intcon_reg_reg_2/CLK (0.9284 0.9236)
cellName = DFFPOSX1
inc_pc_node_reg_3/CLK (0.9293 0.9245)
cellName = DFFPOSX1
inc_pc_node_reg_2/CLK (0.9311 0.9263)
cellName = DFFPOSX1
inc_pc_node_reg_1/CLK (0.9343 0.9295)
cellName = DFFPOSX1
status_reg_reg_2/CLK (0.9289 0.9241)
cellName = DFFPOSX1
ram_i_node_reg_4/CLK (0.9307 0.9259)
cellName = DFFPOSX1
intcon_reg_reg_7/CLK (0.93 0.9252)
cellName = DFFPOSX1
writeram_node_reg/CLK (0.93 0.9252)
cellName = DFFPOSX1
ram_i_node_reg_2/CLK (0.9309 0.9261)
cellName = DFFPOSX1
pc_reg_reg_3/CLK (0.9344 0.9295)
cellName = DFFPOSX1
aluinp1_reg_reg_1/CLK (0.937 0.9324)
cellName = DFFPOSX1
status_reg_reg_0/CLK (0.9383 0.9337)
cellName = DFFPOSX1
aluinp1_reg_reg_0/CLK (0.9379 0.9333)
cellName = DFFPOSX1
inst_reg_reg_7/CLK (0.9326 0.928)
cellName = DFFPOSX1
addlow_node_reg_4/CLK (0.9329 0.9283)
cellName = DFFPOSX1
state_reg_reg_2/CLK (0.9369 0.9323)
cellName = DFFPOSX1
inte_sync_reg_reg/CLK (0.9363 0.9317)
cellName = DFFPOSX1
intclr_reg_reg/CLK (0.9349 0.9303)
cellName = DFFPOSX1
inst_reg_reg_13/CLK (0.9319 0.9273)
cellName = DFFPOSX1
inst_reg_reg_12/CLK (0.9295 0.9249)
cellName = DFFPOSX1
inst_reg_reg_11/CLK (0.9331 0.9285)
cellName = DFFPOSX1
reset_condition_reg/CLK (0.9361 0.9315)
cellName = DFFPOSX1
writew_node_reg/CLK (0.9349 0.9303)
cellName = DFFPOSX1
status_reg_reg_1/CLK (0.9343 0.9297)
cellName = DFFPOSX1
aluinp2_reg_reg_1/CLK (0.9387 0.9341)
cellName = DFFPOSX1
w_reg_reg_0/CLK (0.9349 0.9303)
cellName = DFFPOSX1
aluinp1_reg_reg_6/CLK (0.9537 0.9491)
cellName = DFFPOSX1
w_reg_reg_1/CLK (0.9536 0.949)
cellName = DFFPOSX1
w_reg_reg_2/CLK (0.9472 0.9426)
cellName = DFFPOSX1
w_reg_reg_4/CLK (0.9497 0.9451)
cellName = DFFPOSX1
aluinp2_reg_reg_6/CLK (0.9533 0.9487)
cellName = DFFPOSX1
aluout_zero_node_reg/CLK (0.9532 0.9486)
cellName = DFFPOSX1
option_reg_reg_0/CLK (0.9426 0.938)
cellName = DFFPOSX1
option_reg_reg_1/CLK (0.9431 0.9385)
cellName = DFFPOSX1
aluout_reg_reg_1/CLK (0.9434 0.9388)
cellName = DFFPOSX1
aluout_reg_reg_3/CLK (0.9412 0.9366)
cellName = DFFPOSX1
aluout_reg_reg_4/CLK (0.9429 0.9383)
cellName = DFFPOSX1
aluout_reg_reg_5/CLK (0.9437 0.9391)
cellName = DFFPOSX1
aluout_reg_reg_7/CLK (0.9527 0.9481)
cellName = DFFPOSX1
aluinp1_reg_reg_2/CLK (0.9532 0.9486)
cellName = DFFPOSX1
aluinp1_reg_reg_4/CLK (0.9525 0.9479)
cellName = DFFPOSX1
aluout_reg_reg_2/CLK (0.9448 0.9402)
cellName = DFFPOSX1
aluinp1_reg_reg_5/CLK (0.9541 0.9495)
cellName = DFFPOSX1
aluout_reg_reg_0/CLK (0.9554 0.9502)
cellName = DFFPOSX1
add_node_reg_0/CLK (0.96 0.9548)
cellName = DFFPOSX1
add_node_reg_5/CLK (0.9551 0.9499)
cellName = DFFPOSX1
add_node_reg_4/CLK (0.9563 0.9511)
cellName = DFFPOSX1
add_node_reg_3/CLK (0.9576 0.9524)
cellName = DFFPOSX1
add_node_reg_2/CLK (0.9591 0.9539)
cellName = DFFPOSX1
add_node_reg_1/CLK (0.9598 0.9546)
cellName = DFFPOSX1
aluinp2_reg_reg_0/CLK (0.95 0.9448)
cellName = DFFPOSX1
aluinp2_reg_reg_2/CLK (0.9504 0.9452)
cellName = DFFPOSX1
aluinp2_reg_reg_4/CLK (0.9516 0.9464)
cellName = DFFPOSX1
aluinp2_reg_reg_5/CLK (0.9522 0.947)
cellName = DFFPOSX1
aluinp2_reg_reg_7/CLK (0.9531 0.9479)
cellName = DFFPOSX1
add_node_reg_7/CLK (0.9487 0.9435)
cellName = DFFPOSX1
add_node_reg_8/CLK (0.947 0.9418)
cellName = DFFPOSX1
aluinp1_reg_reg_7/CLK (0.9534 0.9482)
cellName = DFFPOSX1
aluinp2_reg_reg_3/CLK (0.9493 0.9441)
cellName = DFFPOSX1
add_node_reg_6/CLK (0.9525 0.9473)